0x40012400: Analog to Digital Converter
132/146 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | IER | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
| 0xc | CFGR1 | ||||||||||||||||||||||||||||||||
| 0x10 | CFGR2 | ||||||||||||||||||||||||||||||||
| 0x14 | SMPR | ||||||||||||||||||||||||||||||||
| 0x20 | AWD1TR | ||||||||||||||||||||||||||||||||
| 0x24 | AWD2TR | ||||||||||||||||||||||||||||||||
| 0x28 | CHSELR | ||||||||||||||||||||||||||||||||
| 0x28 | CHSELR_1 | ||||||||||||||||||||||||||||||||
| 0x2c | AWD3TR | ||||||||||||||||||||||||||||||||
| 0x40 | DR | ||||||||||||||||||||||||||||||||
| 0xa0 | AWD2CR | ||||||||||||||||||||||||||||||||
| 0xa4 | AWD3CR | ||||||||||||||||||||||||||||||||
| 0xb4 | CALFACT | ||||||||||||||||||||||||||||||||
| 0x308 | CCR | ||||||||||||||||||||||||||||||||
ADC interrupt and status register
Offset: 0x0, reset: 0x00000000, access: Unspecified
10/10 fields covered.
Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..
Allowed values:
0x0: B_0x0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: ADC is ready to start conversion
Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1â..
Allowed values:
0x0: B_0x0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: End of sampling phase reached
Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..
Allowed values:
0x0: B_0x0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Channel conversion complete
Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..
Allowed values:
0x0: B_0x0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Conversion sequence complete
Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..
Allowed values:
0x0: B_0x0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Overrun has occurred
Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..
Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred
Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..
Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred
Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..
Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred
Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..
Allowed values:
0x0: B_0x0: Channel configuration update not applied.
0x1: B_0x1: Channel configuration update is applied.
ADC interrupt enable register
Offset: 0x4, reset: 0x00000000, access: Unspecified
10/10 fields covered.
Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADRDY interrupt disabled.
0x1: B_0x1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: EOSMP interrupt disabled.
0x1: B_0x1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: EOC interrupt disabled
0x1: B_0x1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: EOS interrupt disabled
0x1: B_0x1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Overrun interrupt disabled
0x1: B_0x1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled
Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled
Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled
Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: End of calibration interrupt disabled
0x1: B_0x1: End of calibration interrupt enabled
Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Channel configuration ready interrupt disabled
0x1: B_0x1: Channel configuration ready interrupt enabled
ADC control register
Offset: 0x8, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).
Allowed values:
0x0: B_0x0: ADC is disabled (OFF state)
0x1: B_0x1: Write 1 to enable the ADC.
Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1â is only effective when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
Allowed values:
0x0: B_0x0: No ADDIS command ongoing
0x1: B_0x1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..
Allowed values:
0x0: B_0x0: No ADC conversion is ongoing.
0x1: B_0x1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Bit 4: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1â is only effective when ADSTARTÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC).
Allowed values:
0x0: B_0x0: No ADC stop conversion command ongoing
0x1: B_0x1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0x0: B_0x0: ADC voltage regulator disabled
0x1: B_0x1: ADC voltage regulator enabled
Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Calibration complete
0x1: B_0x1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
ADC configuration register 1
Offset: 0xc, reset: 0x00000000, access: Unspecified
16/16 fields covered.
Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: DMA disabled
0x1: B_0x1: DMA enabled
Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 403 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: DMA one shot mode selected
0x1: B_0x1: DMA circular mode selected
Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Upward scan (from CHSEL0 to CHSEL18)
0x1: B_0x1: Backward scan (from CHSEL18 to CHSEL0)
Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 401 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Right alignment
0x1: B_0x1: Left alignment
Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: TRG0
0x1: B_0x1: TRG1
0x2: B_0x2: TRG2
0x3: B_0x3: TRG3
0x4: B_0x4: TRG4
0x5: B_0x5: TRG5
0x6: B_0x6: TRG6
0x7: B_0x7: TRG7
Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Hardware trigger detection disabled (conversions can be started by software)
0x1: B_0x1: Hardware trigger detection on the rising edge
0x2: B_0x2: Hardware trigger detection on the falling edge
0x3: B_0x3: Hardware trigger detection on both the rising and falling edges
Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC_DR register is preserved with the old data when an overrun is detected.
0x1: B_0x1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Single conversion mode
0x1: B_0x1: Continuous conversion mode
Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Wait conversion mode off
0x1: B_0x1: Wait conversion mode on
Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Auto-off mode disabled
0x1: B_0x1: Auto-off mode enabled
Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Discontinuous mode disabled
0x1: B_0x1: Discontinuous mode enabled
Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Each bit of the ADC_CHSELR register enables an input
0x1: B_0x1: ADC_CHSELR register is able to sequence up to 8 channels
Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Analog watchdog 1 enabled on all channels
0x1: B_0x1: Analog watchdog 1 enabled on a single channel
Bit 23: Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Analog watchdog 1 disabled
0x1: B_0x1: Analog watchdog 1 enabled
Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog input Channel 0 monitored by AWD
0x1: B_0x1: ADC analog input Channel 1 monitored by AWD
0x11: B_0x11: ADC analog input Channel 17 monitored by AWD
0x12: B_0x12: ADC analog input Channel 18 monitored by AWD
ADC configuration register 2
Offset: 0x10, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: 2x
0x1: B_0x1: 4x
0x2: B_0x2: 8x
0x3: B_0x3: 16x
0x4: B_0x4: 32x
0x5: B_0x5: 64x
0x6: B_0x6: 128x
0x7: B_0x7: 256x
Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: No shift
0x1: B_0x1: Shift 1-bit
0x2: B_0x2: Shift 2-bits
0x3: B_0x3: Shift 3-bits
0x4: B_0x4: Shift 4-bits
0x5: B_0x5: Shift 5-bits
0x6: B_0x6: Shift 6-bits
0x7: B_0x7: Shift 7-bits
0x8: B_0x8: Shift 8-bits
Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: All oversampled conversions for a channel are done consecutively after a trigger
0x1: B_0x1: Each oversampled conversion for a channel needs a trigger
Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Low Frequency Trigger Mode disabled
0x1: B_0x1: Low Frequency Trigger Mode enabled
Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0x0: B_0x0: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
0x1: B_0x1: PCLK/2 (Synchronous clock mode)
0x2: B_0x2: PCLK/4 (Synchronous clock mode)
0x3: B_0x3: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)
ADC sampling time register
Offset: 0x14, reset: 0x00000000, access: Unspecified
21/21 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SMPSEL18
rw |
SMPSEL17
rw |
SMPSEL16
rw |
SMPSEL15
rw |
SMPSEL14
rw |
SMPSEL13
rw |
SMPSEL12
rw |
SMPSEL11
rw |
SMPSEL10
rw |
SMPSEL9
rw |
SMPSEL8
rw |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SMPSEL7
rw |
SMPSEL6
rw |
SMPSEL5
rw |
SMPSEL4
rw |
SMPSEL3
rw |
SMPSEL2
rw |
SMPSEL1
rw |
SMPSEL0
rw |
SMP2
rw |
SMP1
rw |
||||||
Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: 1.5 ADC clock cycles
0x1: B_0x1: 3.5 ADC clock cycles
0x2: B_0x2: 7.5 ADC clock cycles
0x3: B_0x3: 12.5 ADC clock cycles
0x4: B_0x4: 19.5 ADC clock cycles
0x5: B_0x5: 39.5 ADC clock cycles
0x6: B_0x6: 79.5 ADC clock cycles
0x7: B_0x7: 160.5 ADC clock cycles
Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: 1.5 ADC clock cycles
0x1: B_0x1: 3.5 ADC clock cycles
0x2: B_0x2: 7.5 ADC clock cycles
0x3: B_0x3: 12.5 ADC clock cycles
0x4: B_0x4: 19.5 ADC clock cycles
0x5: B_0x5: 39.5 ADC clock cycles
0x6: B_0x6: 79.5 ADC clock cycles
0x7: B_0x7: 160.5 ADC clock cycles
Bit 8: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 9: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 10: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 11: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 12: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 13: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 14: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 15: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 16: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 17: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 18: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 19: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 20: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 21: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 22: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 23: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 24: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 25: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
Bit 26: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.
ADC watchdog threshold register
Offset: 0x20, reset: 0x0FFF0000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT1
rw |
|||||||||||||||
ADC watchdog threshold register
Offset: 0x24, reset: 0x0FFF0000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT2
rw |
|||||||||||||||
ADC channel selection register [alternate]
Offset: 0x28, reset: 0x00000000, access: Unspecified
19/19 fields covered.
Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..
Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion
channel selection register CHSELRMOD = 1 in ADC_CFGR1
Offset: 0x28, reset: 0x00000000, access: Unspecified
1/8 fields covered.
Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: CH0
0x1: B_0x1: CH1
0xC: B_0xC: CH12
0xD: B_0xD: CH13
0xE: B_0xE: CH14
0xF: B_0xF: No channel selected (End of sequence)
ADC watchdog threshold register
Offset: 0x2c, reset: 0x0FFF0000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
HT3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LT3
rw |
|||||||||||||||
ADC data register
Offset: 0x40, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DATA
r |
|||||||||||||||
ADC Analog Watchdog 2 Configuration register
Offset: 0xa0, reset: 0x00000000, access: Unspecified
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD2CH18
rw |
AWD2CH17
rw |
AWD2CH16
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD2CH15
rw |
AWD2CH14
rw |
AWD2CH13
rw |
AWD2CH12
rw |
AWD2CH11
rw |
AWD2CH10
rw |
AWD2CH9
rw |
AWD2CH8
rw |
AWD2CH7
rw |
AWD2CH6
rw |
AWD2CH5
rw |
AWD2CH4
rw |
AWD2CH3
rw |
AWD2CH2
rw |
AWD2CH1
rw |
AWD2CH0
rw |
Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2
ADC Analog Watchdog 3 Configuration register
Offset: 0xa4, reset: 0x00000000, access: Unspecified
19/19 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
AWD3CH18
rw |
AWD3CH17
rw |
AWD3CH16
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AWD3CH15
rw |
AWD3CH14
rw |
AWD3CH13
rw |
AWD3CH12
rw |
AWD3CH11
rw |
AWD3CH10
rw |
AWD3CH9
rw |
AWD3CH8
rw |
AWD3CH7
rw |
AWD3CH6
rw |
AWD3CH5
rw |
AWD3CH4
rw |
AWD3CH3
rw |
AWD3CH2
rw |
AWD3CH1
rw |
AWD3CH0
rw |
Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3
ADC Calibration factor
Offset: 0xb4, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALFACT
rw |
|||||||||||||||
Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection..
ADC common configuration register
Offset: 0x308, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
VBATEN
rw |
TSEN
rw |
VREFEN
rw |
PRESC
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..
Allowed values:
0x0: B_0x0: input ADC clock not divided
0x1: B_0x1: input ADC clock divided by 2
0x2: B_0x2: input ADC clock divided by 4
0x3: B_0x3: input ADC clock divided by 6
0x4: B_0x4: input ADC clock divided by 8
0x5: B_0x5: input ADC clock divided by 10
0x6: B_0x6: input ADC clock divided by 12
0x7: B_0x7: input ADC clock divided by 16
0x8: B_0x8: input ADC clock divided by 32
0x9: B_0x9: input ADC clock divided by 64
0xA: B_0xA: input ADC clock divided by 128
0xB: B_0xB: input ADC clock divided by 256
Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..
Allowed values:
0x0: B_0x0: Temperature sensor disabled, DAC_OUT1 connected to ADC channel 12
0x1: B_0x1: Temperature sensor enabled
Bit 24: VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).
Allowed values:
0x0: B_0x0: VBAT channel disabled, DAC_OUT2 connected to ADC channel 14
0x1: B_0x1: VBAT channel enabled
0x40010200: Comparator
33/33 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | COMP1_CSR | ||||||||||||||||||||||||||||||||
| 0x4 | COMP2_CSR | ||||||||||||||||||||||||||||||||
| 0x8 | COMP3_CSR | ||||||||||||||||||||||||||||||||
Comparator 1 control and status register
Offset: 0x0, reset: 0x00000000, access: Unspecified
11/11 fields covered.
Bits 4-7: Comparator 1 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM of the comparator 1: > 1000: 1/4 VREFINT.
Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB1
0x7: B_0x7: PC4
0x8: B_0x8: PA0
Bits 8-9: Comparator 1 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP1_INP of the comparator 1 (also see the WINMODE bit):.
Allowed values:
0x0: B_0x0: PC5
0x1: B_0x1: PB2
0x2: B_0x2: PA1
0x3: B_0x3: None (open)
Bit 11: Comparator 1 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1:.
Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 64)
Bit 31: COMP1_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 1 control register COMP1_CSR[31:0]:.
Allowed values:
0x0: B_0x0: COMP1_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP1_CSR[31:0] register bits can be read but not written by software
Comparator 2 control and status register
Offset: 0x4, reset: 0x00000000, access: Unspecified
11/11 fields covered.
Bits 4-7: Comparator 2 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP2_INM of the comparator 2: > 1000: 1/4 VREFINT.
Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB3
0x7: B_0x7: PB7
0x8: B_0x8: PA2
Bits 8-9: Comparator 2 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP2_INP of the comparator 2 (also see the WINMODE bit):.
Allowed values:
0x0: B_0x0: PB4
0x1: B_0x1: PB6
0x2: B_0x2: PA3
0x3: B_0x3: None (open)
Bit 11: Comparator 2 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP2_INP input of the comparator 2:.
Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 64)
Bit 31: COMP2_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 2 control register COMP2_CSR[31:0]:.
Allowed values:
0x0: B_0x0: COMP2_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP2_CSR[31:0] register bits can be read but not written by software
Comparator 2 control and status register
Offset: 0x8, reset: 0x00000000, access: Unspecified
11/11 fields covered.
Bits 4-7: Comparator 3 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP3_INM of the comparator 3: > 1000: 1/4 VREFINT.
Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB3
0x7: B_0x7: PB7
0x8: B_0x8: PA2
Bits 8-9: Comparator 3 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP3_INP of the comparator 3 (also see the WINMODE bit):.
Allowed values:
0x0: B_0x0: PB4
0x1: B_0x1: PB6
0x2: B_0x2: PA3
0x3: B_0x3: None (open)
Bit 11: Comparator 3 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP3_INP input of the comparator 3:.
Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 64)
Bit 31: COMP3_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 3 control register COMP3_CSR[31:0]:.
Allowed values:
0x0: B_0x0: COMP3_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP3_CSR[31:0] register bits can be read but not written by software
0x40023000: Cyclic redundancy check calculation unit
3/8 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | DR | ||||||||||||||||||||||||||||||||
| 0x4 | IDR | ||||||||||||||||||||||||||||||||
| 0x8 | CR | ||||||||||||||||||||||||||||||||
| 0x10 | INIT | ||||||||||||||||||||||||||||||||
| 0x14 | POL | ||||||||||||||||||||||||||||||||
Data register
Offset: 0x0, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Independent data register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IDR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IDR
rw |
|||||||||||||||
Control register
Offset: 0x8, reset: 0x00000000, access: Unspecified
3/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REV_OUT
rw |
REV_IN
rw |
POLYSIZE
rw |
RESET
w |
||||||||||||
Initial CRC value
Offset: 0x10, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CRC_INIT
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRC_INIT
rw |
|||||||||||||||
polynomial
Offset: 0x14, reset: 0x04C11DB7, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
POL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
POL
rw |
|||||||||||||||
0x40007400: DAC
28/48 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | SWTRGR | ||||||||||||||||||||||||||||||||
| 0x8 | DHR12R1 | ||||||||||||||||||||||||||||||||
| 0xc | DHR12L1 | ||||||||||||||||||||||||||||||||
| 0x10 | DHR8R1 | ||||||||||||||||||||||||||||||||
| 0x14 | DHR12R2 | ||||||||||||||||||||||||||||||||
| 0x18 | DHR12L2 | ||||||||||||||||||||||||||||||||
| 0x1c | DHR8R2 | ||||||||||||||||||||||||||||||||
| 0x20 | DHR12RD | ||||||||||||||||||||||||||||||||
| 0x24 | DHR12LD | ||||||||||||||||||||||||||||||||
| 0x28 | DHR8RD | ||||||||||||||||||||||||||||||||
| 0x2c | DOR1 | ||||||||||||||||||||||||||||||||
| 0x30 | DOR2 | ||||||||||||||||||||||||||||||||
| 0x34 | SR | ||||||||||||||||||||||||||||||||
| 0x38 | CCR | ||||||||||||||||||||||||||||||||
| 0x3c | MCR | ||||||||||||||||||||||||||||||||
| 0x40 | SHSR1 | ||||||||||||||||||||||||||||||||
| 0x44 | SHSR2 | ||||||||||||||||||||||||||||||||
| 0x48 | SHHR | ||||||||||||||||||||||||||||||||
| 0x4c | SHRR | ||||||||||||||||||||||||||||||||
DAC control register
Offset: 0x0, reset: 0x00000000, access: read-write
16/16 fields covered.
Bit 1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle..
Allowed values:
0x0: B_0x0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x1: B_0x1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register
Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..
Allowed values:
0x0: B_0x0: SWTRIG1
0x1: B_0x1: dac_ch1_trg1
0x2: B_0x2: dac_ch1_trg2
0xF: B_0xF: dac_ch1_trg15
Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.
Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
Bit 14: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..
Allowed values:
0x0: B_0x0: DAC channel1 in Normal operating mode
0x1: B_0x1: DAC channel1 in calibration mode
Bit 17: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x1: B_0x1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register
Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: SWTRIG2
0x1: B_0x1: dac_ch2_trg1
0x2: B_0x2: dac_ch2_trg2
0xF: B_0xF: dac_ch2_trg15
Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled
Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: DAC channel2 DMA underrun interrupt disabled
0x1: B_0x1: DAC channel2 DMA underrun interrupt enabled
Bit 30: DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: DAC channel2 in Normal operating mode
0x1: B_0x1: DAC channel2 in calibration mode
DAC software trigger register
Offset: 0x4, reset: 0x00000000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWTRIG2
w |
SWTRIG1
w |
||||||||||||||
Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..
Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger
Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger
DAC channel1 12-bit right-aligned data holding register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DAC channel1 12-bit left aligned data holding register
Offset: 0xc, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DAC channel1 8-bit right aligned data holding register
Offset: 0x10, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DAC channel2 12-bit right aligned data holding register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
DAC channel2 12-bit left aligned data holding register
Offset: 0x18, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
DAC channel2 8-bit right-aligned data holding register
Offset: 0x1c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
|||||||||||||||
Dual DAC 12-bit right-aligned data holding register
Offset: 0x20, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 12-bit left aligned data holding register
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DACC2DHR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DHR
rw |
|||||||||||||||
DUAL DAC 8-bit right aligned data holding register
Offset: 0x28, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DHR
rw |
DACC1DHR
rw |
||||||||||||||
DAC channel1 data output register
Offset: 0x2c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC1DOR
r |
|||||||||||||||
DAC channel2 data output register
Offset: 0x30, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DACC2DOR
r |
|||||||||||||||
DAC status register
Offset: 0x34, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..
Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel1
0x1: B_0x1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 15: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization)..
Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel2
0x1: B_0x1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).
Bit 30: DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value
Bit 31: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation..
Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
DAC calibration control register
Offset: 0x38, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OTRIM2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OTRIM1
rw |
|||||||||||||||
DAC mode control register
Offset: 0x3c, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MODE2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MODE1
rw |
|||||||||||||||
Bits 0-2: DAC channel1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel1 mode: DAC channel1 in Normal mode DAC channel1 in sample & hold mode Note: This register can be modified only when EN1=0..
Allowed values:
0x0: B_0x0: DAC channel1 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x2: B_0x2: DAC channel1 is connected to external pin with Buffer disabled
0x3: B_0x3: DAC channel1 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel1 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel1 is connected to on chip peripherals with Buffer disabled
Bits 16-18: DAC channel2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC channel2 mode: DAC channel2 in Normal mode DAC channel2 in Sample and hold mode Note: This register can be modified only when EN2=0. Refer to for the availability of DAC channel2..
Allowed values:
0x0: B_0x0: DAC channel2 is connected to external pin with Buffer enabled
0x1: B_0x1: DAC channel2 is connected to external pin and to on chip peripherals with buffer enabled
0x2: B_0x2: DAC channel2 is connected to external pin with buffer disabled
0x3: B_0x3: DAC channel2 is connected to on chip peripherals with Buffer disabled
0x4: B_0x4: DAC channel2 is connected to external pin with Buffer enabled
0x5: B_0x5: DAC channel2 is connected to external pin and to on chip peripherals with Buffer enabled
0x6: B_0x6: DAC channel2 is connected to external pin and to on chip peripherals with Buffer disabled
0x7: B_0x7: DAC channel2 is connected to on chip peripherals with Buffer disabled
DAC Sample and Hold sample time register 1
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSAMPLE1
rw |
|||||||||||||||
Bits 0-9: DAC channel1 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If BWST1=1, the write operation is ignored..
DAC Sample and Hold sample time register 2
Offset: 0x44, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSAMPLE2
rw |
|||||||||||||||
Bits 0-9: DAC channel2 sample time (only valid in Sample and hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is low, if BWST2=1, the write operation is ignored..
DAC Sample and Hold hold time register
Offset: 0x48, reset: 0x00010001, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
THOLD2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
THOLD1
rw |
|||||||||||||||
DAC Sample and Hold refresh time register
Offset: 0x4c, reset: 0x00010001, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TREFRESH2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TREFRESH1
rw |
|||||||||||||||
0x40015800: Debug support
19/19 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | IDCODE | ||||||||||||||||||||||||||||||||
| 0x4 | CR | ||||||||||||||||||||||||||||||||
| 0x8 | APB_FZ1 | ||||||||||||||||||||||||||||||||
| 0xc | APB_FZ2 | ||||||||||||||||||||||||||||||||
MCU Device ID Code Register
Offset: 0x0, reset: 0x0, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
REV_ID
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEV_ID
r |
|||||||||||||||
DBG configuration register
Offset: 0x4, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_STANDBY
rw |
DBG_STOP
rw |
||||||||||||||
Bit 1: Debug Stop mode Debug options in Stop mode. Upon Stop mode exit, the software must re-establish the desired clock configuration..
Allowed values:
0x0: B_0x0: All clocks disabled, including FCLK and HCLK. Upon Stop mode exit, the CPU is clocked by the HSI internal RC oscillator.
0x1: B_0x1: FCLK and HCLK running, derived from the internal RC oscillator remaining active. If Systick is enabled, it may generate periodic interrupt and wake up events.
Bit 2: Debug Standby and Shutdown modes Debug options in Standby or Shutdown mode..
Allowed values:
0x0: B_0x0: Digital part powered. From software point of view, exiting Standby and Shutdown modes is identical as fetching reset vector (except for status bits indicating that the MCU exits Standby)
0x1: B_0x1: Digital part powered and FCLK and HCLK running, derived from the internal RC oscillator remaining active. The MCU generates a system reset so that exiting Standby and Shutdown has the same effect as starting from reset.
DBG APB freeze register 1
Offset: 0x8, reset: 0x00000000, access: read-write
10/10 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_LPTIM1_STOP
rw |
DBG_LPTIM2_STOP
rw |
DBG_I2C1_SMBUS_TIMEOUT
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_IWDG_STOP
rw |
DBG_WWDG_STOP
rw |
DBG_RTC_STOP
rw |
DBG_TIM7_STOP
rw |
DBG_TIM6_STOP
rw |
DBG_TIM3_STOP
rw |
DBG_TIM2_STOP
rw |
|||||||||
DBG APB freeze register 2
Offset: 0xc, reset: 0x00000000, access: read-write
5/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DBG_TIM17_STOP
rw |
DBG_TIM16_STOP
rw |
DBG_TIM15_STOP
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBG_TIM14_STOP
rw |
DBG_TIM1_STOP
rw |
||||||||||||||
0x40020000: DMA controller
56/161 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | IFCR | ||||||||||||||||||||||||||||||||
| 0x8 | CR [1] | ||||||||||||||||||||||||||||||||
| 0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
| 0x1c | CR [2] | ||||||||||||||||||||||||||||||||
| 0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
| 0x30 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
| 0x44 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
| 0x6c | CR [6] | ||||||||||||||||||||||||||||||||
| 0x70 | NDTR [6] | ||||||||||||||||||||||||||||||||
| 0x74 | PAR [6] | ||||||||||||||||||||||||||||||||
| 0x78 | MAR [6] | ||||||||||||||||||||||||||||||||
| 0x80 | CR [7] | ||||||||||||||||||||||||||||||||
| 0x84 | NDTR [7] | ||||||||||||||||||||||||||||||||
| 0x88 | PAR [7] | ||||||||||||||||||||||||||||||||
| 0x8c | MAR [7] | ||||||||||||||||||||||||||||||||
low interrupt status register
Offset: 0x0, reset: 0, access: read-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TEIF7
r |
HTIF7
r |
TCIF7
r |
GIF7
r |
TEIF6
r |
HTIF6
r |
TCIF6
r |
GIF6
r |
TEIF5
r |
HTIF5
r |
TCIF5
r |
GIF5
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TEIF4
r |
HTIF4
r |
TCIF4
r |
GIF4
r |
TEIF3
r |
HTIF3
r |
TCIF3
r |
GIF3
r |
TEIF2
r |
HTIF2
r |
TCIF2
r |
GIF2
r |
TEIF1
r |
HTIF1
r |
TCIF1
r |
GIF1
r |
high interrupt status register
Offset: 0x4, reset: 0, access: read-only
28/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CTEIF7
r |
CHTIF7
r |
CTCIF7
r |
CGIF7
r |
CTEIF6
r |
CHTIF6
r |
CTCIF6
r |
CGIF6
r |
CTEIF5
r |
CHTIF5
r |
CTCIF5
r |
CGIF5
r |
||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CTEIF15
r |
CHTIF4
r |
CTCIF4
r |
CGIF4
r |
CTEIF3
r |
CHTIF3
r |
CTCIF3
r |
CGIF3
r |
CTEIF2
r |
CHTIF2
r |
CTCIF2
r |
CGIF2
r |
CTEIF1
r |
CHTIF1
r |
CTCIF1
r |
CGIF1
r |
DMA channel 1 number of data tegister
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x4c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x64, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x70, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x74, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x78, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x84, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x88, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x8c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
0x40020400: DMA controller
40/115 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | IFCR | ||||||||||||||||||||||||||||||||
| 0x8 | CR [1] | ||||||||||||||||||||||||||||||||
| 0xc | NDTR [1] | ||||||||||||||||||||||||||||||||
| 0x10 | PAR [1] | ||||||||||||||||||||||||||||||||
| 0x14 | MAR [1] | ||||||||||||||||||||||||||||||||
| 0x1c | CR [2] | ||||||||||||||||||||||||||||||||
| 0x20 | NDTR [2] | ||||||||||||||||||||||||||||||||
| 0x24 | PAR [2] | ||||||||||||||||||||||||||||||||
| 0x28 | MAR [2] | ||||||||||||||||||||||||||||||||
| 0x30 | CR [3] | ||||||||||||||||||||||||||||||||
| 0x34 | NDTR [3] | ||||||||||||||||||||||||||||||||
| 0x38 | PAR [3] | ||||||||||||||||||||||||||||||||
| 0x3c | MAR [3] | ||||||||||||||||||||||||||||||||
| 0x44 | CR [4] | ||||||||||||||||||||||||||||||||
| 0x48 | NDTR [4] | ||||||||||||||||||||||||||||||||
| 0x4c | PAR [4] | ||||||||||||||||||||||||||||||||
| 0x50 | MAR [4] | ||||||||||||||||||||||||||||||||
| 0x58 | CR [5] | ||||||||||||||||||||||||||||||||
| 0x5c | NDTR [5] | ||||||||||||||||||||||||||||||||
| 0x60 | PAR [5] | ||||||||||||||||||||||||||||||||
| 0x64 | MAR [5] | ||||||||||||||||||||||||||||||||
DMA channel 1 number of data tegister
Offset: 0xc, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x10, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x14, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x20, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x24, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x28, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x34, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x38, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x3c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x48, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x4c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x50, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
DMA channel 1 number of data tegister
Offset: 0x5c, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NDT
rw |
|||||||||||||||
DMA channel 1 peripheral address
Offset: 0x60, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PA
rw |
|||||||||||||||
DMA channel 1 memory address
Offset: 0x64, reset: 0, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MA
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MA
rw |
|||||||||||||||
0x40020800: DMAMUX
51/91 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | C0CR | ||||||||||||||||||||||||||||||||
| 0x4 | C1CR | ||||||||||||||||||||||||||||||||
| 0x8 | C2CR | ||||||||||||||||||||||||||||||||
| 0xc | C3CR | ||||||||||||||||||||||||||||||||
| 0x10 | C4CR | ||||||||||||||||||||||||||||||||
| 0x14 | C5CR | ||||||||||||||||||||||||||||||||
| 0x18 | C6CR | ||||||||||||||||||||||||||||||||
| 0x80 | CSR | ||||||||||||||||||||||||||||||||
| 0x84 | CFR | ||||||||||||||||||||||||||||||||
| 0x100 | RG0CR | ||||||||||||||||||||||||||||||||
| 0x104 | RG1CR | ||||||||||||||||||||||||||||||||
| 0x108 | RG2CR | ||||||||||||||||||||||||||||||||
| 0x10c | RG3CR | ||||||||||||||||||||||||||||||||
| 0x140 | RGSR | ||||||||||||||||||||||||||||||||
| 0x144 | RGCFR | ||||||||||||||||||||||||||||||||
DMAMUX request generator interrupt status register
Offset: 0x140, reset: 0x00000000, access: read-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OF3
r |
OF2
r |
OF1
r |
OF0
r |
||||||||||||
Bit 0: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 1: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 2: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
Bit 3: Trigger overrun event flag The flag is set when a new trigger event occurs on DMA request generator channel x, before the request counter underrun (the internal request counter programmed via the GNBREQ field of the DMAMUX_RGxCR register). The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR register..
DMAMUX request generator interrupt clear flag register
Offset: 0x144, reset: 0x00000000, access: write-only
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
COF3
w |
COF2
w |
COF1
w |
COF0
w |
||||||||||||
0x40021800: External interrupt/event controller
190/190 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | RTSR1 | ||||||||||||||||||||||||||||||||
| 0x4 | FTSR1 | ||||||||||||||||||||||||||||||||
| 0x8 | SWIER1 | ||||||||||||||||||||||||||||||||
| 0xc | RPR1 | ||||||||||||||||||||||||||||||||
| 0x10 | FPR1 | ||||||||||||||||||||||||||||||||
| 0x28 | RTSR2 | ||||||||||||||||||||||||||||||||
| 0x2c | FTSR2 | ||||||||||||||||||||||||||||||||
| 0x30 | SWIER2 | ||||||||||||||||||||||||||||||||
| 0x34 | RPR2 | ||||||||||||||||||||||||||||||||
| 0x38 | FPR2 | ||||||||||||||||||||||||||||||||
| 0x60 | EXTICR1 | ||||||||||||||||||||||||||||||||
| 0x64 | EXTICR2 | ||||||||||||||||||||||||||||||||
| 0x68 | EXTICR3 | ||||||||||||||||||||||||||||||||
| 0x6c | EXTICR4 | ||||||||||||||||||||||||||||||||
| 0x80 | IMR1 | ||||||||||||||||||||||||||||||||
| 0x84 | EMR1 | ||||||||||||||||||||||||||||||||
| 0x90 | IMR2 | ||||||||||||||||||||||||||||||||
| 0x94 | EMR2 | ||||||||||||||||||||||||||||||||
EXTI rising trigger selection register 2
Offset: 0x28, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RT2
rw |
|||||||||||||||
EXTI falling trigger selection register 2
Offset: 0x2c, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FT2
rw |
|||||||||||||||
EXTI software interrupt event register 2
Offset: 0x30, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SWI2
rw |
|||||||||||||||
EXTI rising edge pending register 2
Offset: 0x34, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RPIF2
rw |
|||||||||||||||
EXTI falling edge pending register 2
Offset: 0x38, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FPIF2
rw |
|||||||||||||||
EXTI external interrupt selection register
Offset: 0x60, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EXTI24_31
rw |
EXTI16_23
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI8_15
rw |
EXTI0_7
rw |
||||||||||||||
EXTI external interrupt selection register
Offset: 0x64, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EXTI24_31
rw |
EXTI16_23
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI8_15
rw |
EXTI0_7
rw |
||||||||||||||
EXTI external interrupt selection register
Offset: 0x68, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EXTI24_31
rw |
EXTI16_23
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI8_15
rw |
EXTI0_7
rw |
||||||||||||||
EXTI external interrupt selection register
Offset: 0x6c, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EXTI24_31
rw |
EXTI16_23
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EXTI8_15
rw |
EXTI0_7
rw |
||||||||||||||
EXTI CPU wakeup with interrupt mask register
Offset: 0x80, reset: 0xFFF80000, access: read-write
32/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IM31
rw |
IM30
rw |
IM29
rw |
IM28
rw |
IM27
rw |
IM26
rw |
IM25
rw |
IM24
rw |
IM23
rw |
IM22
rw |
IM21
rw |
IM20
rw |
IM19
rw |
IM18
rw |
IM17
rw |
IM16
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IM15
rw |
IM14
rw |
IM13
rw |
IM12
rw |
IM11
rw |
IM10
rw |
IM9
rw |
IM8
rw |
IM7
rw |
IM6
rw |
IM5
rw |
IM4
rw |
IM3
rw |
IM2
rw |
IM1
rw |
IM0
rw |
EXTI CPU wakeup with event mask register
Offset: 0x84, reset: 0x00000000, access: read-write
29/29 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EM31
rw |
EM30
rw |
EM29
rw |
EM28
rw |
EM27
rw |
EM26
rw |
EM25
rw |
EM23
rw |
EM21
rw |
EM19
rw |
EM18
rw |
EM17
rw |
EM16
rw |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EM15
rw |
EM14
rw |
EM13
rw |
EM12
rw |
EM11
rw |
EM10
rw |
EM9
rw |
EM8
rw |
EM7
rw |
EM6
rw |
EM5
rw |
EM4
rw |
EM3
rw |
EM2
rw |
EM1
rw |
EM0
rw |
EXTI CPU wakeup with interrupt mask register
Offset: 0x90, reset: 0xFFFFFFFF, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IM35
rw |
IM34
rw |
IM33
rw |
IM32
rw |
||||||||||||
EXTI CPU wakeup with event mask register
Offset: 0x94, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EM35
rw |
EM34
rw |
EM33
rw |
EM32
rw |
||||||||||||
0x40006400: FD controller area network
127/160 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CREL | ||||||||||||||||||||||||||||||||
| 0x4 | ENDN | ||||||||||||||||||||||||||||||||
| 0xc | DBTP | ||||||||||||||||||||||||||||||||
| 0x10 | TEST | ||||||||||||||||||||||||||||||||
| 0x14 | RWD | ||||||||||||||||||||||||||||||||
| 0x18 | CCCR | ||||||||||||||||||||||||||||||||
| 0x1c | NBTP | ||||||||||||||||||||||||||||||||
| 0x20 | TSCC | ||||||||||||||||||||||||||||||||
| 0x24 | TSCV | ||||||||||||||||||||||||||||||||
| 0x28 | TOCC | ||||||||||||||||||||||||||||||||
| 0x2c | TOCV | ||||||||||||||||||||||||||||||||
| 0x40 | ECR | ||||||||||||||||||||||||||||||||
| 0x44 | PSR | ||||||||||||||||||||||||||||||||
| 0x48 | TDCR | ||||||||||||||||||||||||||||||||
| 0x50 | IR | ||||||||||||||||||||||||||||||||
| 0x54 | IE | ||||||||||||||||||||||||||||||||
| 0x58 | ILS | ||||||||||||||||||||||||||||||||
| 0x5c | ILE | ||||||||||||||||||||||||||||||||
| 0x80 | RXGFC | ||||||||||||||||||||||||||||||||
| 0x84 | XIDAM | ||||||||||||||||||||||||||||||||
| 0x88 | HPMS | ||||||||||||||||||||||||||||||||
| 0x90 | RXF0S | ||||||||||||||||||||||||||||||||
| 0x94 | RXF0A | ||||||||||||||||||||||||||||||||
| 0x98 | RXF1S | ||||||||||||||||||||||||||||||||
| 0x9c | RXF1A | ||||||||||||||||||||||||||||||||
| 0xc0 | TXBC | ||||||||||||||||||||||||||||||||
| 0xc4 | TXFQS | ||||||||||||||||||||||||||||||||
| 0xc8 | TXBRP | ||||||||||||||||||||||||||||||||
| 0xcc | TXBAR | ||||||||||||||||||||||||||||||||
| 0xd0 | TXBCR | ||||||||||||||||||||||||||||||||
| 0xd4 | TXBTO | ||||||||||||||||||||||||||||||||
| 0xd8 | TXBCF | ||||||||||||||||||||||||||||||||
| 0xdc | TXBTIE | ||||||||||||||||||||||||||||||||
| 0xe0 | TXBCIE | ||||||||||||||||||||||||||||||||
| 0xe4 | TXEFS | ||||||||||||||||||||||||||||||||
| 0xe8 | TXEFA | ||||||||||||||||||||||||||||||||
| 0x100 | CKDIV | ||||||||||||||||||||||||||||||||
FDCAN endian register
Offset: 0x4, reset: 0x87654321, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ETV
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ETV
r |
|||||||||||||||
FDCAN data bit timing and prescaler register
Offset: 0xc, reset: 0x00000A33, access: Unspecified
1/5 fields covered.
Bits 16-20: Data bit rate prescaler The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1..
FDCAN test register
Offset: 0x10, reset: 0x00000000, access: Unspecified
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RX
r |
TX
rw |
LBCK
rw |
|||||||||||||
Bits 5-6: Control of transmit pin.
Allowed values:
0x0: B_0x0: Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time
0x1: B_0x1: Sample point can be monitored at pin FDCANx_TX
0x2: B_0x2: Dominant (0) level at pin FDCANx_TX
0x3: B_0x3: Recessive (1) at pin FDCANx_TX
FDCAN RAM watchdog register
Offset: 0x14, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDV
r |
WDC
rw |
||||||||||||||
FDCAN CC control register
Offset: 0x18, reset: 0x00000001, access: Unspecified
14/14 fields covered.
Bit 2: ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time..
Allowed values:
0x0: B_0x0: Normal CAN operation
0x1: B_0x1: Restricted Operation Mode active
FDCAN nominal bit timing and prescaler register
Offset: 0x1c, reset: 0x06000A03, access: Unspecified
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NSJW
rw |
NBRP
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NTSEG1
rw |
NTSEG2
rw |
||||||||||||||
Bits 8-15: Nominal time segment before sample point Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 16-24: Bit rate prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 25-31: Nominal (re)synchronization jump width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN timestamp counter configuration register
Offset: 0x20, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TCP
rw |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSS
rw |
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Bits 0-1: Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Timestamp counter value always 0x0000
0x1: B_0x1: Timestamp counter value incremented according to TCP
0x2: B_0x2: External timestamp counter from TIM3 value (tim3_cnt[0:15])
0x3: B_0x3: Same as 00.
Bits 16-19: Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 ⦠16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN timestamp counter value register
Offset: 0x24, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSC
rw |
|||||||||||||||
Bits 0-15: Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1 ⦠16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact..
FDCAN timeout counter configuration register
Offset: 0x28, reset: 0xFFFF0000, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TOP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TOS
rw |
ETOC
rw |
||||||||||||||
Bits 1-2: Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Continuous operation
0x1: B_0x1: Timeout controlled by Tx Event FIFO
0x2: B_0x2: Timeout controlled by Rx FIFO 0
0x3: B_0x3: Timeout controlled by Rx FIFO 1
FDCAN timeout counter value register
Offset: 0x2c, reset: 0x0000FFFF, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TOC
rw |
|||||||||||||||
Bits 0-15: Timeout counter The timeout counter is decremented in multiples of CAN bit times [1 ⦠16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS..
FDCAN error counter register
Offset: 0x40, reset: 0x00000000, access: Unspecified
3/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RP
r |
REC
r |
TEC
r |
|||||||||||||
Bits 16-23: CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read..
FDCAN protocol status register
Offset: 0x44, reset: 0x00000707, access: Unspecified
10/11 fields covered.
Bits 0-2: Last error code The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read..
Allowed values:
0x0: B_0x0: No Error: No error occurred since LEC has been reset by successful reception or transmission.
0x1: B_0x1: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2: B_0x2: Form Error: A fixed format part of a received frame has the wrong format.
0x3: B_0x3: AckError: The message transmitted by the FDCAN was not acknowledged by another node.
0x4: B_0x4: Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.
0x5: B_0x5: Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6: B_0x6: CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
0x7: B_0x7: NoChange: Any read access to the Protocol status register re-initializes the LEC to '7â. When the LEC shows the value '7â, no CAN bus event was detected since the last CPU read access to the Protocol status register.
Bits 3-4: Activity Monitors the moduleâs CAN communication state..
Allowed values:
0x0: B_0x0: Synchronizing: node is synchronizing on CAN communication.
0x1: B_0x1: Idle: node is neither receiver nor transmitter.
0x2: B_0x2: Receiver: node is operating as receiver.
0x3: B_0x3: Transmitter: node is operating as transmitter.
Bits 8-10: Data last error code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read..
Bit 11: ESI flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read..
Allowed values:
0x0: B_0x0: Last received FDCAN message did not have its ESI flag set.
0x1: B_0x1: Last received FDCAN message had its ESI flag set.
Bit 12: BRS flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read..
Allowed values:
0x0: B_0x0: Last received FDCAN message did not have its BRS flag set.
0x1: B_0x1: Last received FDCAN message had its BRS flag set.
Bits 16-22: Transmitter delay compensation value Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq..
FDCAN transmitter delay compensation register
Offset: 0x48, reset: 0x00000000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDCO
rw |
TDCF
rw |
||||||||||||||
Bits 0-6: Transmitter delay compensation filter window length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 8-14: Transmitter delay compensation offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN interrupt register
Offset: 0x50, reset: 0x00000000, access: Unspecified
24/24 fields covered.
Bit 14: Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted Operation Mode (see mode). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM..
Allowed values:
0x0: B_0x0: No Message RAM access failure occurred
0x1: B_0x1: Message RAM access failure occurred
FDCAN interrupt line enable register
Offset: 0x5c, reset: 0x00000000, access: Unspecified
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EINT1
rw |
EINT0
rw |
||||||||||||||
FDCAN global filter configuration register
Offset: 0x80, reset: 0x00000000, access: Unspecified
6/8 fields covered.
Bit 0: Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Filter remote frames with 29-bit standard IDs
0x1: B_0x1: Reject all remote frames with 29-bit standard IDs
Bit 1: Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Filter remote frames with 11-bit standard IDs
0x1: B_0x1: Reject all remote frames with 11-bit standard IDs
Bits 2-3: Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Accept in Rx FIFO 0
0x1: B_0x1: Accept in Rx FIFO 1
0x2: B_0x2: Reject
0x3: B_0x3: Reject
Bits 4-5: Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Accept in Rx FIFO 0
0x1: B_0x1: Accept in Rx FIFO 1
0x2: B_0x2: Reject
0x3: B_0x3: Reject
Bits 16-20: List size standard >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: No standard message ID filter
0x1: B_0x1: Number of standard message ID filter elements
0x2: B_0x2: Number of standard message ID filter elements
0x3: B_0x3: Number of standard message ID filter elements
0x4: B_0x4: Number of standard message ID filter elements
0x5: B_0x5: Number of standard message ID filter elements
0x6: B_0x6: Number of standard message ID filter elements
0x7: B_0x7: Number of standard message ID filter elements
0x8: B_0x8: Number of standard message ID filter elements
0x9: B_0x9: Number of standard message ID filter elements
0xa: B_0xa: Number of standard message ID filter elements
0xb: B_0xb: Number of standard message ID filter elements
0xc: B_0xc: Number of standard message ID filter elements
0xd: B_0xd: Number of standard message ID filter elements
0xe: B_0xe: Number of standard message ID filter elements
0xf: B_0xf: Number of standard message ID filter elements
0x10: B_0x10: Number of standard message ID filter elements
0x11: B_0x11: Number of standard message ID filter elements
0x12: B_0x12: Number of standard message ID filter elements
0x13: B_0x13: Number of standard message ID filter elements
0x14: B_0x14: Number of standard message ID filter elements
0x15: B_0x15: Number of standard message ID filter elements
0x16: B_0x16: Number of standard message ID filter elements
0x17: B_0x17: Number of standard message ID filter elements
0x18: B_0x18: Number of standard message ID filter elements
0x19: B_0x19: Number of standard message ID filter elements
0x1a: B_0x1a: Number of standard message ID filter elements
0x1b: B_0x1b: Number of standard message ID filter elements
0x1c: B_0x1c: Number of standard message ID filter elements
Bits 24-27: List size extended >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: No extended message ID filter
0x1: B_0x1: Number of extended message ID filter elements
0x2: B_0x2: Number of extended message ID filter elements
0x3: B_0x3: Number of extended message ID filter elements
0x4: B_0x4: Number of extended message ID filter elements
0x5: B_0x5: Number of extended message ID filter elements
0x6: B_0x6: Number of extended message ID filter elements
0x7: B_0x7: Number of extended message ID filter elements
0x8: B_0x8: Number of extended message ID filter elements
FDCAN extended ID and mask register
Offset: 0x84, reset: 0x1FFFFFFF, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EIDM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EIDM
rw |
|||||||||||||||
Bits 0-28: Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN high-priority message status register
Offset: 0x88, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FLST
r |
FIDX
r |
MSI
r |
BIDX
r |
||||||||||||
CAN Rx FIFO 0 acknowledge register
Offset: 0x94, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F0AI
rw |
|||||||||||||||
Bits 0-2: Rx FIFO 0 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFOÂ 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]..
FDCAN Rx FIFO 1 acknowledge register
Offset: 0x9c, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F1AI
rw |
|||||||||||||||
Bits 0-2: Rx FIFO 1 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFOÂ 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]..
FDCAN Tx buffer configuration register
Offset: 0xc0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TFQM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDCAN Tx FIFO/queue status register
Offset: 0xc4, reset: 0x00000003, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TFQF
r |
TFQPI
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TFGI
r |
TFFL
r |
||||||||||||||
FDCAN Tx buffer request pending register
Offset: 0xc8, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRP
r |
|||||||||||||||
Bits 0-2: Transmission request pending Each Tx Buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions..
Allowed values:
0x0: B_0x0: No transmission request pending
0x1: B_0x1: Transmission request pending
FDCAN Tx buffer add request register
Offset: 0xcc, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AR
rw |
|||||||||||||||
Bits 0-2: Add request Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed..
Allowed values:
0x0: B_0x0: No transmission request added
0x1: B_0x1: Transmission requested added.
FDCAN Tx buffer cancellation request register
Offset: 0xd0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CR
rw |
|||||||||||||||
Bits 0-2: Cancellation request Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset..
Allowed values:
0x0: B_0x0: No cancellation pending
0x1: B_0x1: Cancellation pending
FDCAN Tx buffer transmission occurred register
Offset: 0xd4, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TO
r |
|||||||||||||||
Bits 0-2: Transmission occurred. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR..
Allowed values:
0x0: B_0x0: No transmission occurred
0x1: B_0x1: Transmission occurred
FDCAN Tx buffer cancellation finished register
Offset: 0xd8, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CF
r |
|||||||||||||||
Bits 0-2: Cancellation finished Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR..
Allowed values:
0x0: B_0x0: No transmit buffer cancellation
0x1: B_0x1: Transmit buffer cancellation finished
FDCAN Tx buffer transmission interrupt enable register
Offset: 0xdc, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIE
rw |
|||||||||||||||
FDCAN Tx buffer cancellation finished interrupt enable register
Offset: 0xe0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CFIE
rw |
|||||||||||||||
FDCAN Tx event FIFO acknowledge register
Offset: 0xe8, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EFAI
rw |
|||||||||||||||
Bits 0-1: Event FIFO acknowledge index After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]..
FDCAN CFG clock divider register
Offset: 0x100, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PDIV
rw |
|||||||||||||||
Bits 0-3: input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Divide by 1
0x1: B_0x1: Divide by 2
0x2: B_0x2: Divide by 4
0x3: B_0x3: Divide by 6
0x4: B_0x4: Divide by 8
0x5: B_0x5: Divide by 10
0x6: B_0x6: Divide by 12
0x7: B_0x7: Divide by 14
0x8: B_0x8: Divide by 16
0x9: B_0x9: Divide by 18
0xA: B_0xA: Divide by 20
0xB: B_0xB: Divide by 22
0xC: B_0xC: Divide by 24
0xD: B_0xD: Divide by 26
0xE: B_0xE: Divide by 28
0xF: B_0xF: Divide by 30
0x40006800: FD controller area network
127/160 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CREL | ||||||||||||||||||||||||||||||||
| 0x4 | ENDN | ||||||||||||||||||||||||||||||||
| 0xc | DBTP | ||||||||||||||||||||||||||||||||
| 0x10 | TEST | ||||||||||||||||||||||||||||||||
| 0x14 | RWD | ||||||||||||||||||||||||||||||||
| 0x18 | CCCR | ||||||||||||||||||||||||||||||||
| 0x1c | NBTP | ||||||||||||||||||||||||||||||||
| 0x20 | TSCC | ||||||||||||||||||||||||||||||||
| 0x24 | TSCV | ||||||||||||||||||||||||||||||||
| 0x28 | TOCC | ||||||||||||||||||||||||||||||||
| 0x2c | TOCV | ||||||||||||||||||||||||||||||||
| 0x40 | ECR | ||||||||||||||||||||||||||||||||
| 0x44 | PSR | ||||||||||||||||||||||||||||||||
| 0x48 | TDCR | ||||||||||||||||||||||||||||||||
| 0x50 | IR | ||||||||||||||||||||||||||||||||
| 0x54 | IE | ||||||||||||||||||||||||||||||||
| 0x58 | ILS | ||||||||||||||||||||||||||||||||
| 0x5c | ILE | ||||||||||||||||||||||||||||||||
| 0x80 | RXGFC | ||||||||||||||||||||||||||||||||
| 0x84 | XIDAM | ||||||||||||||||||||||||||||||||
| 0x88 | HPMS | ||||||||||||||||||||||||||||||||
| 0x90 | RXF0S | ||||||||||||||||||||||||||||||||
| 0x94 | RXF0A | ||||||||||||||||||||||||||||||||
| 0x98 | RXF1S | ||||||||||||||||||||||||||||||||
| 0x9c | RXF1A | ||||||||||||||||||||||||||||||||
| 0xc0 | TXBC | ||||||||||||||||||||||||||||||||
| 0xc4 | TXFQS | ||||||||||||||||||||||||||||||||
| 0xc8 | TXBRP | ||||||||||||||||||||||||||||||||
| 0xcc | TXBAR | ||||||||||||||||||||||||||||||||
| 0xd0 | TXBCR | ||||||||||||||||||||||||||||||||
| 0xd4 | TXBTO | ||||||||||||||||||||||||||||||||
| 0xd8 | TXBCF | ||||||||||||||||||||||||||||||||
| 0xdc | TXBTIE | ||||||||||||||||||||||||||||||||
| 0xe0 | TXBCIE | ||||||||||||||||||||||||||||||||
| 0xe4 | TXEFS | ||||||||||||||||||||||||||||||||
| 0xe8 | TXEFA | ||||||||||||||||||||||||||||||||
| 0x100 | CKDIV | ||||||||||||||||||||||||||||||||
FDCAN endian register
Offset: 0x4, reset: 0x87654321, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ETV
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ETV
r |
|||||||||||||||
FDCAN data bit timing and prescaler register
Offset: 0xc, reset: 0x00000A33, access: Unspecified
1/5 fields covered.
Bits 16-20: Data bit rate prescaler The value by which the oscillator frequency is divided to generate the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are 0 to 31. The hardware interpreters this value as the value programmed plus 1..
FDCAN test register
Offset: 0x10, reset: 0x00000000, access: Unspecified
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RX
r |
TX
rw |
LBCK
rw |
|||||||||||||
Bits 5-6: Control of transmit pin.
Allowed values:
0x0: B_0x0: Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the CAN bit time
0x1: B_0x1: Sample point can be monitored at pin FDCANx_TX
0x2: B_0x2: Dominant (0) level at pin FDCANx_TX
0x3: B_0x3: Recessive (1) at pin FDCANx_TX
FDCAN RAM watchdog register
Offset: 0x14, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDV
r |
WDC
rw |
||||||||||||||
FDCAN CC control register
Offset: 0x18, reset: 0x00000001, access: Unspecified
14/14 fields covered.
Bit 2: ASM restricted operation mode The restricted operation mode is intended for applications that adapt themselves to different CAN bit rates. The application tests different bit rates and leaves the Restricted Operation Mode after it has received a valid frame. In the optional Restricted Operation Mode the node is able to transmit and receive data and remote frames and it gives acknowledge to valid frames, but it does not send active error frames or overload frames. In case of an error condition or overload condition, it does not send dominant bits, instead it waits for the occurrence of bus idle condition to resynchronize itself to the CAN communication. The error counters are not incremented. Bit ASM can only be set by software when both CCE and INIT are set to 1. The bit can be reset by the software at any time..
Allowed values:
0x0: B_0x0: Normal CAN operation
0x1: B_0x1: Restricted Operation Mode active
FDCAN nominal bit timing and prescaler register
Offset: 0x1c, reset: 0x06000A03, access: Unspecified
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
NSJW
rw |
NBRP
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
NTSEG1
rw |
NTSEG2
rw |
||||||||||||||
Bits 8-15: Nominal time segment before sample point Valid values are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 16-24: Bit rate prescaler Value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 25-31: Nominal (re)synchronization jump width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that the used value is the one programmed incremented by one. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN timestamp counter configuration register
Offset: 0x20, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TCP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSS
rw |
|||||||||||||||
Bits 0-1: Timestamp select These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Timestamp counter value always 0x0000
0x1: B_0x1: Timestamp counter value incremented according to TCP
0x2: B_0x2: External timestamp counter from TIM3 value (tim3_cnt[0:15])
0x3: B_0x3: Same as 00.
Bits 16-19: Timestamp counter prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1 ⦠16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. In CAN FD mode the internal timestamp counter TCP does not provide a constant time base due to the different CAN bit times between arbitration phase and data phase. Thus CAN FD requires an external counter for timestamp generation (TSS = 10). These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN timestamp counter value register
Offset: 0x24, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSC
rw |
|||||||||||||||
Bits 0-15: Timestamp counter The internal/external timestamp counter value is captured on start of frame (both Rx and Tx). When TSCC[TSS] = 01, the timestamp counter is incremented in multiples of CAN bit times [1 ⦠16] depending on the configuration of TSCC[TCP]. A wrap around sets interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC reflects the external timestamp counter value. A write access has no impact..
FDCAN timeout counter configuration register
Offset: 0x28, reset: 0xFFFF0000, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TOP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TOS
rw |
ETOC
rw |
||||||||||||||
Bits 1-2: Timeout select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Continuous operation
0x1: B_0x1: Timeout controlled by Tx Event FIFO
0x2: B_0x2: Timeout controlled by Rx FIFO 0
0x3: B_0x3: Timeout controlled by Rx FIFO 1
FDCAN timeout counter value register
Offset: 0x2c, reset: 0x0000FFFF, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TOC
rw |
|||||||||||||||
Bits 0-15: Timeout counter The timeout counter is decremented in multiples of CAN bit times [1 ⦠16] depending on the configuration of TSCC.TCP. When decremented to 0, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS..
FDCAN error counter register
Offset: 0x40, reset: 0x00000000, access: Unspecified
3/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RP
r |
REC
r |
TEC
r |
|||||||||||||
Bits 16-23: CAN error logging The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read..
FDCAN protocol status register
Offset: 0x44, reset: 0x00000707, access: Unspecified
10/11 fields covered.
Bits 0-2: Last error code The LEC indicates the type of the last error to occur on the CAN bus. This field is cleared to 0 when a message has been transferred (reception or transmission) without error. Access type is RS: set on read..
Allowed values:
0x0: B_0x0: No Error: No error occurred since LEC has been reset by successful reception or transmission.
0x1: B_0x1: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2: B_0x2: Form Error: A fixed format part of a received frame has the wrong format.
0x3: B_0x3: AckError: The message transmitted by the FDCAN was not acknowledged by another node.
0x4: B_0x4: Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.
0x5: B_0x5: Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6: B_0x6: CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data.
0x7: B_0x7: NoChange: Any read access to the Protocol status register re-initializes the LEC to '7â. When the LEC shows the value '7â, no CAN bus event was detected since the last CPU read access to the Protocol status register.
Bits 3-4: Activity Monitors the moduleâs CAN communication state..
Allowed values:
0x0: B_0x0: Synchronizing: node is synchronizing on CAN communication.
0x1: B_0x1: Idle: node is neither receiver nor transmitter.
0x2: B_0x2: Receiver: node is operating as receiver.
0x3: B_0x3: Transmitter: node is operating as transmitter.
Bits 8-10: Data last error code Type of last error that occurred in the data phase of a FDCAN format frame with its BRS flag set. Coding is the same as for LEC. This field is cleared to 0 when a FDCAN format frame with its BRS flag set has been transferred (reception or transmission) without error. Access type is RS: set on read..
Bit 11: ESI flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read..
Allowed values:
0x0: B_0x0: Last received FDCAN message did not have its ESI flag set.
0x1: B_0x1: Last received FDCAN message had its ESI flag set.
Bit 12: BRS flag of last received FDCAN message This bit is set together with REDL, independent of acceptance filtering. Access type is RX: reset on read..
Allowed values:
0x0: B_0x0: Last received FDCAN message did not have its BRS flag set.
0x1: B_0x1: Last received FDCAN message had its BRS flag set.
Bits 16-22: Transmitter delay compensation value Position of the secondary sample point, defined by the sum of the measured delay from FDCAN_TX to FDCAN_RX and TDCR.TDCO. The SSP position is, in the data phase, the number of minimum time quanta (mtq) between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq..
FDCAN transmitter delay compensation register
Offset: 0x48, reset: 0x00000000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDCO
rw |
TDCF
rw |
||||||||||||||
Bits 0-6: Transmitter delay compensation filter window length Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that would result in an earlier SSP position are ignored for transmitter delay measurements. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Bits 8-14: Transmitter delay compensation offset Offset value defining the distance between the measured delay from FDCAN_TX to FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN interrupt register
Offset: 0x50, reset: 0x00000000, access: Unspecified
24/24 fields covered.
Bit 14: Message RAM access failure The flag is set when the Rx handler: has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. was unable to write a message to the message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated. The partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the FDCAN is switched into Restricted Operation Mode (see mode). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM..
Allowed values:
0x0: B_0x0: No Message RAM access failure occurred
0x1: B_0x1: Message RAM access failure occurred
FDCAN interrupt line enable register
Offset: 0x5c, reset: 0x00000000, access: Unspecified
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EINT1
rw |
EINT0
rw |
||||||||||||||
FDCAN global filter configuration register
Offset: 0x80, reset: 0x00000000, access: Unspecified
6/8 fields covered.
Bit 0: Reject remote frames extended These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Filter remote frames with 29-bit standard IDs
0x1: B_0x1: Reject all remote frames with 29-bit standard IDs
Bit 1: Reject remote frames standard These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Filter remote frames with 11-bit standard IDs
0x1: B_0x1: Reject all remote frames with 11-bit standard IDs
Bits 2-3: Accept non-matching frames extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Accept in Rx FIFO 0
0x1: B_0x1: Accept in Rx FIFO 1
0x2: B_0x2: Reject
0x3: B_0x3: Reject
Bits 4-5: Accept Non-matching frames standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Accept in Rx FIFO 0
0x1: B_0x1: Accept in Rx FIFO 1
0x2: B_0x2: Reject
0x3: B_0x3: Reject
Bits 16-20: List size standard >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: No standard message ID filter
0x1: B_0x1: Number of standard message ID filter elements
0x2: B_0x2: Number of standard message ID filter elements
0x3: B_0x3: Number of standard message ID filter elements
0x4: B_0x4: Number of standard message ID filter elements
0x5: B_0x5: Number of standard message ID filter elements
0x6: B_0x6: Number of standard message ID filter elements
0x7: B_0x7: Number of standard message ID filter elements
0x8: B_0x8: Number of standard message ID filter elements
0x9: B_0x9: Number of standard message ID filter elements
0xa: B_0xa: Number of standard message ID filter elements
0xb: B_0xb: Number of standard message ID filter elements
0xc: B_0xc: Number of standard message ID filter elements
0xd: B_0xd: Number of standard message ID filter elements
0xe: B_0xe: Number of standard message ID filter elements
0xf: B_0xf: Number of standard message ID filter elements
0x10: B_0x10: Number of standard message ID filter elements
0x11: B_0x11: Number of standard message ID filter elements
0x12: B_0x12: Number of standard message ID filter elements
0x13: B_0x13: Number of standard message ID filter elements
0x14: B_0x14: Number of standard message ID filter elements
0x15: B_0x15: Number of standard message ID filter elements
0x16: B_0x16: Number of standard message ID filter elements
0x17: B_0x17: Number of standard message ID filter elements
0x18: B_0x18: Number of standard message ID filter elements
0x19: B_0x19: Number of standard message ID filter elements
0x1a: B_0x1a: Number of standard message ID filter elements
0x1b: B_0x1b: Number of standard message ID filter elements
0x1c: B_0x1c: Number of standard message ID filter elements
Bits 24-27: List size extended >8: Values greater than 8 are interpreted as 8. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: No extended message ID filter
0x1: B_0x1: Number of extended message ID filter elements
0x2: B_0x2: Number of extended message ID filter elements
0x3: B_0x3: Number of extended message ID filter elements
0x4: B_0x4: Number of extended message ID filter elements
0x5: B_0x5: Number of extended message ID filter elements
0x6: B_0x6: Number of extended message ID filter elements
0x7: B_0x7: Number of extended message ID filter elements
0x8: B_0x8: Number of extended message ID filter elements
FDCAN extended ID and mask register
Offset: 0x84, reset: 0x1FFFFFFF, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
EIDM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EIDM
rw |
|||||||||||||||
Bits 0-28: Extended ID mask For acceptance filtering of extended frames the Extended ID AND Mask is AND-ed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to 1 the mask is not active. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
FDCAN high-priority message status register
Offset: 0x88, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
FLST
r |
FIDX
r |
MSI
r |
BIDX
r |
||||||||||||
CAN Rx FIFO 0 acknowledge register
Offset: 0x94, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F0AI
rw |
|||||||||||||||
Bits 0-2: Rx FIFO 0 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This sets the Rx FIFOÂ 0 get index RXF0S[F0GI] to F0AI + 1 and update the FIFO 0 fill level RXF0S[F0FL]..
FDCAN Rx FIFO 1 acknowledge register
Offset: 0x9c, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
F1AI
rw |
|||||||||||||||
Bits 0-2: Rx FIFO 1 acknowledge index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This sets the Rx FIFOÂ 1 get index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level RXF1S[F1FL]..
FDCAN Tx buffer configuration register
Offset: 0xc0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TFQM
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDCAN Tx FIFO/queue status register
Offset: 0xc4, reset: 0x00000003, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TFQF
r |
TFQPI
r |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TFGI
r |
TFFL
r |
||||||||||||||
FDCAN Tx buffer request pending register
Offset: 0xc8, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRP
r |
|||||||||||||||
Bits 0-2: Transmission request pending Each Tx Buffer has its own transmission request pending bit. The bits are set via register TXBAR. The bits are reset after a requested transmission has completed or has been canceled via register TXBCR. After a TXBRP bit has been set, a Tx scan is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signaled via TXBCF after successful transmission together with the corresponding TXBTO bit when the transmission has not yet been started at the point of cancellation when the transmission has been aborted due to lost arbitration when an error occurred during frame transmission In DAR mode all transmissions are automatically canceled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions..
Allowed values:
0x0: B_0x0: No transmission request pending
0x1: B_0x1: Transmission request pending
FDCAN Tx buffer add request register
Offset: 0xcc, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
AR
rw |
|||||||||||||||
Bits 0-2: Add request Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed..
Allowed values:
0x0: B_0x0: No transmission request added
0x1: B_0x1: Transmission requested added.
FDCAN Tx buffer cancellation request register
Offset: 0xd0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CR
rw |
|||||||||||||||
Bits 0-2: Cancellation request Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit; writing a 0 has no impact. This enables the Host to set cancellation requests for multiple Tx buffers with one write to TXBCR. The bits remain set until the corresponding TXBRP bit is reset..
Allowed values:
0x0: B_0x0: No cancellation pending
0x1: B_0x1: Cancellation pending
FDCAN Tx buffer transmission occurred register
Offset: 0xd4, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TO
r |
|||||||||||||||
Bits 0-2: Transmission occurred. Each Tx buffer has its own TO bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR..
Allowed values:
0x0: B_0x0: No transmission occurred
0x1: B_0x1: Transmission occurred
FDCAN Tx buffer cancellation finished register
Offset: 0xd8, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CF
r |
|||||||||||||||
Bits 0-2: Cancellation finished Each Tx buffer has its own CF bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a 1 to the corresponding bit of register TXBAR..
Allowed values:
0x0: B_0x0: No transmit buffer cancellation
0x1: B_0x1: Transmit buffer cancellation finished
FDCAN Tx buffer transmission interrupt enable register
Offset: 0xdc, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIE
rw |
|||||||||||||||
FDCAN Tx buffer cancellation finished interrupt enable register
Offset: 0xe0, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CFIE
rw |
|||||||||||||||
FDCAN Tx event FIFO acknowledge register
Offset: 0xe8, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EFAI
rw |
|||||||||||||||
Bits 0-1: Event FIFO acknowledge index After the Host has read an element or a sequence of elements from the Tx event FIFO, it has to write the index of the last element read from Tx event FIFO to EFAI. This sets the Tx event FIFO get index TXEFS[EFGI] to EFAI + 1 and updates the FIFO 0 fill level TXEFS[EFFL]..
FDCAN CFG clock divider register
Offset: 0x100, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PDIV
rw |
|||||||||||||||
Bits 0-3: input clock divider The APB clock could be divided prior to be used by the CAN sub system. The rate must be computed using the divider output clock. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1..
Allowed values:
0x0: B_0x0: Divide by 1
0x1: B_0x1: Divide by 2
0x2: B_0x2: Divide by 4
0x3: B_0x3: Divide by 6
0x4: B_0x4: Divide by 8
0x5: B_0x5: Divide by 10
0x6: B_0x6: Divide by 12
0x7: B_0x7: Divide by 14
0x8: B_0x8: Divide by 16
0x9: B_0x9: Divide by 18
0xA: B_0xA: Divide by 20
0xB: B_0xB: Divide by 22
0xC: B_0xC: Divide by 24
0xD: B_0xD: Divide by 26
0xE: B_0xE: Divide by 28
0xF: B_0xF: Divide by 30
0x40022000: Flash
10/77 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ACR | ||||||||||||||||||||||||||||||||
| 0x8 | KEYR | ||||||||||||||||||||||||||||||||
| 0xc | OPTKEYR | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | CR | ||||||||||||||||||||||||||||||||
| 0x18 | ECCR | ||||||||||||||||||||||||||||||||
| 0x20 | OPTR | ||||||||||||||||||||||||||||||||
| 0x24 | PCROP1ASR | ||||||||||||||||||||||||||||||||
| 0x28 | PCROP1AER | ||||||||||||||||||||||||||||||||
| 0x2c | WRP1AR | ||||||||||||||||||||||||||||||||
| 0x30 | WRP1BR | ||||||||||||||||||||||||||||||||
| 0x34 | PCROP1BSR | ||||||||||||||||||||||||||||||||
| 0x38 | PCROP1BER | ||||||||||||||||||||||||||||||||
| 0x44 | PCROP2ASR | ||||||||||||||||||||||||||||||||
| 0x48 | PCROP2AER | ||||||||||||||||||||||||||||||||
| 0x4c | WRP2AR | ||||||||||||||||||||||||||||||||
| 0x50 | WRP2BR | ||||||||||||||||||||||||||||||||
| 0x54 | PCROP2BSR | ||||||||||||||||||||||||||||||||
| 0x58 | PCROP2BER | ||||||||||||||||||||||||||||||||
| 0x80 | SECR | ||||||||||||||||||||||||||||||||
Flash key register
Offset: 0x8, reset: 0x00000000, access: write-only
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
KEYR
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEYR
w |
|||||||||||||||
Option byte key register
Offset: 0xc, reset: 0x00000000, access: write-only
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OPTKEYR
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OPTKEYR
w |
|||||||||||||||
Flash option register
Offset: 0x20, reset: 0xF0000000, access: read-write
0/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
IRHEN
rw |
NRST_MODE
rw |
nBOOT0
rw |
nBOOT1
rw |
nBOOT_SEL
rw |
RAM_PARITY_CHECK
rw |
WWDG_SW
rw |
IWDG_STDBY
rw |
IWDG_STOP
rw |
IDWG_SW
rw |
||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
nRSTS_HDW
rw |
nRST_STDBY
rw |
nRST_STOP
rw |
BORR_LEV
rw |
BORF_LEV
rw |
BOREN
rw |
RDP
rw |
|||||||||
Flash PCROP zone A Start address register
Offset: 0x24, reset: 0xF0000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP1A_STRT
r |
|||||||||||||||
Flash PCROP zone A End address register
Offset: 0x28, reset: 0xF0000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PCROP_RDP
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP1A_END
r |
|||||||||||||||
Flash WRP area A address register
Offset: 0x2c, reset: 0xF0000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WRP1A_END
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WRP1A_STRT
r |
|||||||||||||||
Flash WRP area B address register
Offset: 0x30, reset: 0xF0000000, access: read-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WRP1B_END
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WRP1B_STRT
r |
|||||||||||||||
Flash PCROP zone B Start address register
Offset: 0x34, reset: 0xF0000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP1B_STRT
r |
|||||||||||||||
Flash PCROP area B End address register
Offset: 0x38, reset: 0xF0000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP1B_END
rw |
|||||||||||||||
Flash PCROP2 area A start address register
Offset: 0x44, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP2A_STRT
rw |
|||||||||||||||
Flash PCROP2 area A end address register
Offset: 0x48, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP2A_END
rw |
|||||||||||||||
Flash WRP2 area A address register
Offset: 0x4c, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WRP2A_END
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WRP2A_STRT
rw |
|||||||||||||||
Flash WRP2 area B address register
Offset: 0x50, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
WRP2B_END
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WRP2B_STRT
rw |
|||||||||||||||
FLASH PCROP2 area B start address register
Offset: 0x54, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP2B_STRT
rw |
|||||||||||||||
FLASH PCROP2 area B end address register
Offset: 0x58, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PCROP2B_END
rw |
|||||||||||||||
Flash Security register
Offset: 0x80, reset: 0xF0000000, access: read-write
0/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
SEC_SIZE2
rw |
BOOT_LOCK
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SEC_SIZE
rw |
|||||||||||||||
0x50000000: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50000400: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50000800: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50000c00: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50001000: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x50001400: General-purpose I/Os
16/177 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | MODER | ||||||||||||||||||||||||||||||||
| 0x4 | OTYPER | ||||||||||||||||||||||||||||||||
| 0x8 | OSPEEDR | ||||||||||||||||||||||||||||||||
| 0xc | PUPDR | ||||||||||||||||||||||||||||||||
| 0x10 | IDR | ||||||||||||||||||||||||||||||||
| 0x14 | ODR | ||||||||||||||||||||||||||||||||
| 0x18 | BSRR | ||||||||||||||||||||||||||||||||
| 0x1c | LCKR | ||||||||||||||||||||||||||||||||
| 0x20 | AFRL | ||||||||||||||||||||||||||||||||
| 0x24 | AFRH | ||||||||||||||||||||||||||||||||
| 0x28 | BRR | ||||||||||||||||||||||||||||||||
GPIO port bit set/reset register
Offset: 0x18, reset: 0x00000000, access: write-only
0/32 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BR15
w |
BR14
w |
BR13
w |
BR12
w |
BR11
w |
BR10
w |
BR9
w |
BR8
w |
BR7
w |
BR6
w |
BR5
w |
BR4
w |
BR3
w |
BR2
w |
BR1
w |
BR0
w |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BS15
w |
BS14
w |
BS13
w |
BS12
w |
BS11
w |
BS10
w |
BS9
w |
BS8
w |
BS7
w |
BS6
w |
BS5
w |
BS4
w |
BS3
w |
BS2
w |
BS1
w |
BS0
w |
0x40007800: HDMI-CEC
25/40 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CEC_CR | ||||||||||||||||||||||||||||||||
| 0x4 | CEC_CFGR | ||||||||||||||||||||||||||||||||
| 0x8 | CEC_TXDR | ||||||||||||||||||||||||||||||||
| 0xc | CEC_RXDR | ||||||||||||||||||||||||||||||||
| 0x10 | CEC_ISR | ||||||||||||||||||||||||||||||||
| 0x14 | CEC_IER | ||||||||||||||||||||||||||||||||
CEC control register
Offset: 0x0, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXEOM
rw |
TXSOM
rw |
CECEN
rw |
|||||||||||||
Bit 0: CEC enable The CECEN bit is set and cleared by software. CECEN = 1 starts message reception and enables the TXSOM control. CECEN = 0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission..
Allowed values:
0x0: B_0x0: CEC peripheral is off.
0x1: B_0x1: CEC peripheral is on.
Bit 1: Tx start of message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission starts after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND = 1), in case of transmission underrun (TXUDR = 1), negative acknowledge (TXACKE = 1), and transmission error (TXERR = 1). It is also cleared by CECEN = 0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST = 1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN = 1. TXSOM must be set when transmission data is available into TXDR. HEADER first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR that is used only for reception..
Allowed values:
0x0: B_0x0: No CEC transmission is on-going
0x1: B_0x1: CEC transmission command
Bit 2: Tx end of message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN = 1. TXEOM must be set before writing transmission data to TXDR. If TXEOM is set when TXSOM = 0, transmitted message consists of 1 byte (HEADER) only (PING message)..
Allowed values:
0x0: B_0x0: TXDR data byte is transmitted with EOM = 0
0x1: B_0x1: TXDR data byte is transmitted with EOM = 1
This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0.
Offset: 0x4, reset: 0x00000000, access: read-write
8/9 fields covered.
Bits 0-2: Signal free time SFT bits are set by software. In the SFT = 0x0 configuration, the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. 0x0 2.5 data-bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1) 4 data-bit periods if CEC is the new bus initiator 6 data-bit periods if CEC is the last bus initiator with successful transmission (TXEOM = 1).
Allowed values:
0x1: B_0x1: 0.5 nominal data bit periods
0x2: B_0x2: 1.5 nominal data bit periods
0x3: B_0x3: 2.5 nominal data bit periods
0x4: B_0x4: 3.5 nominal data bit periods
0x5: B_0x5: 4.5 nominal data bit periods
0x6: B_0x6: 5.5 nominal data bit periods
0x7: B_0x7: 6.5 nominal data bit periods
Bit 3: Rx-tolerance The RXTOL bit is set and cleared by software. Start-bit, +/- 200 µs rise, +/- 200 µs fall Data-bit: +/- 200 µs rise. +/- 350 µs fall Start-bit: +/- 400 µs rise, +/- 400 µs fall Data-bit: +/-300 µs rise, +/- 500 µs fall.
Allowed values:
0x0: B_0x0: Standard tolerance margin:
0x1: B_0x1: Extended tolerance
Bit 5: Generate error-bit on bit rising error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon BRE detection with BRESTP = 1 in broadcast even if BREGEN = 0..
Allowed values:
0x0: B_0x0: BRE detection does not generate an error-bit on the CEC line.
0x1: B_0x1: BRE detection generates an error-bit on the CEC line (if BRESTP is set).
Bit 6: Generate error-bit on long bit period error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN = 0, an error-bit is generated upon LBPE detection in broadcast even if LBPEGEN = 0..
Allowed values:
0x0: B_0x0: LBPE detection does not generate an error-bit on the CEC line.
0x1: B_0x1: LBPE detection generates an error-bit on the CEC line.
Bit 7: Avoid error-bit generation in broadcast The BRDNOGEN bit is set and cleared by software. error-bit on the CEC line. LBPE detection with LBPEGEN = 0 on a broadcast message generates an error-bit on the CEC line..
Allowed values:
0x0: B_0x0: BRE detection with BRESTP = 1 and BREGEN = 0 on a broadcast message generates an
0x1: B_0x1: Error-bit is not generated in the same condition as above. An error-bit is not generated even in case of an SBPE detection in a broadcast message if listen mode is set.
Bits 16-30: Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN = 1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received..
Bit 31: Listen mode LSTN bit is set and cleared by software..
Allowed values:
0x0: B_0x0: CEC peripheral receives only message addressed to its own address (OAR). Messages addressed to different destination are ignored. Broadcast messages are always received.
0x1: B_0x1: CEC peripheral receives messages addressed to its own address (OAR) with positive acknowledge. Messages addressed to different destination are received, but without interfering with the CEC bus: no acknowledge sent.
CEC Tx data register
Offset: 0x8, reset: 0x00000000, access: write-only
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXD
w |
|||||||||||||||
CEC Rx Data Register
Offset: 0xc, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXD
r |
|||||||||||||||
CEC Interrupt and Status Register
Offset: 0x10, reset: 0x00000000, access: read-write
0/13 fields covered.
Bit 2: Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1..
Bit 3: Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1..
Bit 5: Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1..
Bit 6: Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1..
Bit 7: Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1..
Bit 8: Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1..
Bit 12: Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1..
0x40005400: Inter-integrated circuit
53/76 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x00000000, access: read-write
20/20 fields covered.
Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..
Allowed values:
0x0: B_0x0: Peripheral disable
0x1: B_0x1: Peripheral enable
Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).
Allowed values:
0x0: B_0x0: Error detection interrupts disabled
0x1: B_0x1: Error detection interrupts enabled
Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Digital filter disabled
0x1: B_0x1: Digital filter enabled and filtering capability up to 1 tI2CCLK
0xF: B_0xF: digital filter enabled and filtering capability up to15 tI2CCLK
Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Clock stretching enabled
0x1: B_0x1: Clock stretching disabled
Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â.
Allowed values:
0x0: B_0x0: Wakeup from Stop mode disable.
0x1: B_0x1: Wakeup from Stop mode enable.
Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: Device Default Address disabled. Address 0b1100001x is NACKed.
0x1: B_0x1: Device Default Address enabled. Address 0b1100001x is ACKed.
Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x1: B_0x1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).
Control register 2
Offset: 0x4, reset: 0x00000000, access: read-write
9/11 fields covered.
Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..
Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0x0: B_0x0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x1: B_0x1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..
Allowed values:
0x0: B_0x0: No Start generation.
0x1: B_0x1: Restart/Start generation:
Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect..
Allowed values:
0x0: B_0x0: No Stop generation.
0x1: B_0x1: Stop generation after current byte transfer.
Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..
Allowed values:
0x0: B_0x0: an ACK is sent after current received byte.
0x1: B_0x1: a NACK is sent after current received byte.
Bit 24: NBYTES reload mode This bit is set and cleared by software..
Allowed values:
0x0: B_0x0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x1: B_0x1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.
Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..
Allowed values:
0x0: B_0x0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x1: B_0x1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: No PEC transfer.
0x1: B_0x1: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xc, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..
Allowed values:
0x0: B_0x0: No mask
0x1: B_0x1: OA2[1] is masked and donât care. Only OA2[7:2] are compared.
0x2: B_0x2: OA2[2:1] are masked and donât care. Only OA2[7:3] are compared.
0x3: B_0x3: OA2[3:1] are masked and donât care. Only OA2[7:4] are compared.
0x4: B_0x4: OA2[4:1] are masked and donât care. Only OA2[7:5] are compared.
0x5: B_0x5: OA2[5:1] are masked and donât care. Only OA2[7:6] are compared.
0x6: B_0x6: OA2[6:1] are masked and donât care. Only OA2[7] is compared.
0x7: B_0x7: OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.
Status register 1
Offset: 0x14, reset: 0x00000000, access: read-write
3/5 fields covered.
Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..
Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40005800: Inter-integrated circuit
53/76 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x00000000, access: read-write
20/20 fields covered.
Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..
Allowed values:
0x0: B_0x0: Peripheral disable
0x1: B_0x1: Peripheral enable
Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).
Allowed values:
0x0: B_0x0: Error detection interrupts disabled
0x1: B_0x1: Error detection interrupts enabled
Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Digital filter disabled
0x1: B_0x1: Digital filter enabled and filtering capability up to 1 tI2CCLK
0xF: B_0xF: digital filter enabled and filtering capability up to15 tI2CCLK
Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Clock stretching enabled
0x1: B_0x1: Clock stretching disabled
Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â.
Allowed values:
0x0: B_0x0: Wakeup from Stop mode disable.
0x1: B_0x1: Wakeup from Stop mode enable.
Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: Device Default Address disabled. Address 0b1100001x is NACKed.
0x1: B_0x1: Device Default Address enabled. Address 0b1100001x is ACKed.
Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x1: B_0x1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).
Control register 2
Offset: 0x4, reset: 0x00000000, access: read-write
9/11 fields covered.
Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..
Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0x0: B_0x0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x1: B_0x1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..
Allowed values:
0x0: B_0x0: No Start generation.
0x1: B_0x1: Restart/Start generation:
Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect..
Allowed values:
0x0: B_0x0: No Stop generation.
0x1: B_0x1: Stop generation after current byte transfer.
Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..
Allowed values:
0x0: B_0x0: an ACK is sent after current received byte.
0x1: B_0x1: a NACK is sent after current received byte.
Bit 24: NBYTES reload mode This bit is set and cleared by software..
Allowed values:
0x0: B_0x0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x1: B_0x1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.
Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..
Allowed values:
0x0: B_0x0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x1: B_0x1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: No PEC transfer.
0x1: B_0x1: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xc, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..
Allowed values:
0x0: B_0x0: No mask
0x1: B_0x1: OA2[1] is masked and donât care. Only OA2[7:2] are compared.
0x2: B_0x2: OA2[2:1] are masked and donât care. Only OA2[7:3] are compared.
0x3: B_0x3: OA2[3:1] are masked and donât care. Only OA2[7:4] are compared.
0x4: B_0x4: OA2[4:1] are masked and donât care. Only OA2[7:5] are compared.
0x5: B_0x5: OA2[5:1] are masked and donât care. Only OA2[7:6] are compared.
0x6: B_0x6: OA2[6:1] are masked and donât care. Only OA2[7] is compared.
0x7: B_0x7: OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.
Status register 1
Offset: 0x14, reset: 0x00000000, access: read-write
3/5 fields covered.
Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..
Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40008800: Inter-integrated circuit
53/76 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | OAR1 | ||||||||||||||||||||||||||||||||
| 0xc | OAR2 | ||||||||||||||||||||||||||||||||
| 0x10 | TIMINGR | ||||||||||||||||||||||||||||||||
| 0x14 | TIMEOUTR | ||||||||||||||||||||||||||||||||
| 0x18 | ISR | ||||||||||||||||||||||||||||||||
| 0x1c | ICR | ||||||||||||||||||||||||||||||||
| 0x20 | PECR | ||||||||||||||||||||||||||||||||
| 0x24 | RXDR | ||||||||||||||||||||||||||||||||
| 0x28 | TXDR | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x00000000, access: read-write
20/20 fields covered.
Bit 0: Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles..
Allowed values:
0x0: B_0x0: Peripheral disable
0x1: B_0x1: Peripheral enable
Bit 7: Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT).
Allowed values:
0x0: B_0x0: Error detection interrupts disabled
0x1: B_0x1: Error detection interrupts enabled
Bits 8-11: Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Digital filter disabled
0x1: B_0x1: Digital filter enabled and filtering capability up to 1 tI2CCLK
0xF: B_0xF: digital filter enabled and filtering capability up to15 tI2CCLK
Bit 17: Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)..
Allowed values:
0x0: B_0x0: Clock stretching enabled
0x1: B_0x1: Clock stretching disabled
Bit 18: Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to . Note: WUPEN can be set only when DNF = '0000â.
Allowed values:
0x0: B_0x0: Wakeup from Stop mode disable.
0x1: B_0x1: Wakeup from Stop mode enable.
Bit 21: SMBus Device Default Address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: Device Default Address disabled. Address 0b1100001x is NACKed.
0x1: B_0x1: Device Default Address enabled. Address 0b1100001x is ACKed.
Bit 22: SMBus alert enable Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled (0001100x followed by NACK).
0x1: B_0x1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode (SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is enabled (0001100x followed by ACK).
Control register 2
Offset: 0x4, reset: 0x00000000, access: read-write
9/11 fields covered.
Bits 0-9: Slave address (master mode) In 7-bit addressing mode (ADD10 = 0): SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9], SADD[8] and SADD[0] are don't care. In 10-bit addressing mode (ADD10 = 1): SADD[9:0] should be written with the 10-bit slave address to be sent. Note: Changing these bits when the START bit is set is not allowed..
Bit 12: 10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed..
Allowed values:
0x0: B_0x0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
0x1: B_0x1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Bit 13: Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing '1â to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit generates a START condition once the bus is free. Note: Writing '0â to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set..
Allowed values:
0x0: B_0x0: No Start generation.
0x1: B_0x1: Restart/Start generation:
Bit 14: Stop generation (master mode) The bit is set by software, cleared by hardware when a STOP condition is detected, or when PE = 0. In Master Mode: Note: Writing '0â to this bit has no effect..
Allowed values:
0x0: B_0x0: No Stop generation.
0x1: B_0x1: Stop generation after current byte transfer.
Bit 15: NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing '0â to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value..
Allowed values:
0x0: B_0x0: an ACK is sent after current received byte.
0x1: B_0x1: a NACK is sent after current received byte.
Bit 24: NBYTES reload mode This bit is set and cleared by software..
Allowed values:
0x0: B_0x0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
0x1: B_0x1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.
Bit 25: Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set..
Allowed values:
0x0: B_0x0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
0x1: B_0x1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
Bit 26: Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing '0â to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0â. Refer to ..
Allowed values:
0x0: B_0x0: No PEC transfer.
0x1: B_0x1: PEC transmission/reception is requested
Own address register 1
Offset: 0x8, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA1EN
rw |
OA1MODE
rw |
OA1
rw |
|||||||||||||
Own address register 2
Offset: 0xc, reset: 0x00000000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OA2EN
rw |
OA2MSK
rw |
OA2
rw |
|||||||||||||
Bits 8-10: Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches..
Allowed values:
0x0: B_0x0: No mask
0x1: B_0x1: OA2[1] is masked and donât care. Only OA2[7:2] are compared.
0x2: B_0x2: OA2[2:1] are masked and donât care. Only OA2[7:3] are compared.
0x3: B_0x3: OA2[3:1] are masked and donât care. Only OA2[7:4] are compared.
0x4: B_0x4: OA2[4:1] are masked and donât care. Only OA2[7:5] are compared.
0x5: B_0x5: OA2[5:1] are masked and donât care. Only OA2[7:6] are compared.
0x6: B_0x6: OA2[6:1] are masked and donât care. Only OA2[7] is compared.
0x7: B_0x7: OA2[7:1] are masked and donât care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.
Status register 1
Offset: 0x14, reset: 0x00000000, access: read-write
3/5 fields covered.
Bits 0-11: Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0..
Bits 16-27: Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0..
PEC register
Offset: 0x20, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PEC
r |
|||||||||||||||
Receive data register
Offset: 0x24, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
0x40003000: Independent watchdog
4/7 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | KR | ||||||||||||||||||||||||||||||||
| 0x4 | PR | ||||||||||||||||||||||||||||||||
| 0x8 | RLR | ||||||||||||||||||||||||||||||||
| 0xc | SR | ||||||||||||||||||||||||||||||||
| 0x10 | WINR | ||||||||||||||||||||||||||||||||
Key register
Offset: 0x0, reset: 0x00000000, access: write-only
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
Prescaler register
Offset: 0x4, reset: 0x00000000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PR
rw |
|||||||||||||||
Bits 0-2: Prescaler divider These bits are write access protected see . They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the status register (IWDG_SR) is reset..
Allowed values:
0x0: B_0x0: divider /4
0x1: B_0x1: divider /8
0x2: B_0x2: divider /16
0x3: B_0x3: divider /32
0x4: B_0x4: divider /64
0x5: B_0x5: divider /128
0x6: B_0x6: divider /256
0x7: B_0x7: divider /256
Reload register
Offset: 0x8, reset: 0x00000FFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RL
rw |
|||||||||||||||
Status register
Offset: 0xc, reset: 0x00000000, access: read-only
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WVU
r |
RVU
r |
PVU
r |
|||||||||||||
Bit 0: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Prescaler value can be updated only when PVU bit is reset..
Bit 1: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Reload value can be updated only when RVU bit is reset..
Bit 2: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to five LSI cycles). Window value can be updated only when WVU bit is reset..
Window register
Offset: 0x10, reset: 0x00000FFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WIN
rw |
|||||||||||||||
0x40007c00: Low power timer
31/44 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | ICR | ||||||||||||||||||||||||||||||||
| 0x8 | IER | ||||||||||||||||||||||||||||||||
| 0xc | CFGR | ||||||||||||||||||||||||||||||||
| 0x10 | CR | ||||||||||||||||||||||||||||||||
| 0x14 | CMP | ||||||||||||||||||||||||||||||||
| 0x18 | ARR | ||||||||||||||||||||||||||||||||
| 0x1c | CNT | ||||||||||||||||||||||||||||||||
| 0x24 | CFGR2 | ||||||||||||||||||||||||||||||||
Interrupt and Status Register
Offset: 0x0, reset: 0x00000000, access: read-only
7/7 fields covered.
Bit 2: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register..
Bit 5: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..
Bit 6: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..
Configuration Register
Offset: 0xc, reset: 0x00000000, access: read-write
13/13 fields covered.
Bits 1-2: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes..
Allowed values:
0x0: B_0x0: the rising edge is the active edge used for counting.
0x1: B_0x1: the falling edge is the active edge used for counting
0x2: B_0x2: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x3: B_0x3: not allowed
Bits 3-4: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
Allowed values:
0x0: B_0x0: any external clock signal level change is considered as a valid transition
0x1: B_0x1: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x2: B_0x2: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x3: B_0x3: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.
Bits 6-7: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.
Allowed values:
0x0: B_0x0: any trigger active level change is considered as a valid trigger
0x1: B_0x1: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x2: B_0x2: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x3: B_0x3: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.
Bits 13-15: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details..
Allowed values:
0x0: B_0x0: lptim_ext_trig0
0x1: B_0x1: lptim_ext_trig1
0x2: B_0x2: lptim_ext_trig2
0x3: B_0x3: lptim_ext_trig3
0x4: B_0x4: lptim_ext_trig4
0x5: B_0x5: lptim_ext_trig5
0x6: B_0x6: lptim_ext_trig6
0x7: B_0x7: lptim_ext_trig7
Bits 17-18: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.
Allowed values:
0x0: B_0x0: software trigger (counting start is initiated by software)
0x1: B_0x1: rising edge is the active edge
0x2: B_0x2: falling edge is the active edge
0x3: B_0x3: both edges are active edges
Bit 21: Waveform shape polarity The WAVEPOL bit controls the output polarity.
Allowed values:
0x0: B_0x0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1: B_0x1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers
Bit 23: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.
Allowed values:
0x0: B_0x0: the counter is incremented following each internal clock pulse
0x1: B_0x1: the counter is incremented following each valid clock pulse on the LPTIM external Input1
Control Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/5 fields covered.
Bit 1: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware..
Bit 2: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware..
Bit 3: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'..
Compare Register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP
rw |
|||||||||||||||
Autoreload Register
Offset: 0x18, reset: 0x00000001, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
Counter Register
Offset: 0x1c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
r |
|||||||||||||||
LPTIM configuration register 2
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IN2SEL
rw |
IN1SEL
rw |
||||||||||||||
Bits 0-1: LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to ..
Allowed values:
0x0: B_0x0: lptim_in1_mux0
0x1: B_0x1: lptim_in1_mux1
0x2: B_0x2: lptim_in1_mux2
0x3: B_0x3: lptim_in1_mux3
Bits 4-5: LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to ..
Allowed values:
0x0: B_0x0: lptim_in2_mux0
0x1: B_0x1: lptim_in2_mux1
0x2: B_0x2: lptim_in2_mux2
0x3: B_0x3: lptim_in2_mux3
0x40009400: Low power timer
31/44 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | ISR | ||||||||||||||||||||||||||||||||
| 0x4 | ICR | ||||||||||||||||||||||||||||||||
| 0x8 | IER | ||||||||||||||||||||||||||||||||
| 0xc | CFGR | ||||||||||||||||||||||||||||||||
| 0x10 | CR | ||||||||||||||||||||||||||||||||
| 0x14 | CMP | ||||||||||||||||||||||||||||||||
| 0x18 | ARR | ||||||||||||||||||||||||||||||||
| 0x1c | CNT | ||||||||||||||||||||||||||||||||
| 0x24 | CFGR2 | ||||||||||||||||||||||||||||||||
Interrupt and Status Register
Offset: 0x0, reset: 0x00000000, access: read-only
7/7 fields covered.
Bit 2: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register..
Bit 5: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..
Bit 6: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to ..
Configuration Register
Offset: 0xc, reset: 0x00000000, access: read-write
13/13 fields covered.
Bits 1-2: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes..
Allowed values:
0x0: B_0x0: the rising edge is the active edge used for counting.
0x1: B_0x1: the falling edge is the active edge used for counting
0x2: B_0x2: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency.If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
0x3: B_0x3: not allowed
Bits 3-4: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature.
Allowed values:
0x0: B_0x0: any external clock signal level change is considered as a valid transition
0x1: B_0x1: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition.
0x2: B_0x2: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition.
0x3: B_0x3: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition.
Bits 6-7: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature.
Allowed values:
0x0: B_0x0: any trigger active level change is considered as a valid trigger
0x1: B_0x1: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger.
0x2: B_0x2: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger.
0x3: B_0x3: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger.
Bits 13-15: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: See for details..
Allowed values:
0x0: B_0x0: lptim_ext_trig0
0x1: B_0x1: lptim_ext_trig1
0x2: B_0x2: lptim_ext_trig2
0x3: B_0x3: lptim_ext_trig3
0x4: B_0x4: lptim_ext_trig4
0x5: B_0x5: lptim_ext_trig5
0x6: B_0x6: lptim_ext_trig6
0x7: B_0x7: lptim_ext_trig7
Bits 17-18: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:.
Allowed values:
0x0: B_0x0: software trigger (counting start is initiated by software)
0x1: B_0x1: rising edge is the active edge
0x2: B_0x2: falling edge is the active edge
0x3: B_0x3: both edges are active edges
Bit 21: Waveform shape polarity The WAVEPOL bit controls the output polarity.
Allowed values:
0x0: B_0x0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP registers
0x1: B_0x1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and LPTIM_CMP registers
Bit 23: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:.
Allowed values:
0x0: B_0x0: the counter is incremented following each internal clock pulse
0x1: B_0x1: the counter is incremented following each valid clock pulse on the LPTIM external Input1
Control Register
Offset: 0x10, reset: 0x00000000, access: read-write
1/5 fields covered.
Bit 1: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware..
Bit 2: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = '00â), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than '00â), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware..
Bit 3: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit will trigger a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'..
Compare Register
Offset: 0x14, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CMP
rw |
|||||||||||||||
Autoreload Register
Offset: 0x18, reset: 0x00000001, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
Counter Register
Offset: 0x1c, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
r |
|||||||||||||||
LPTIM configuration register 2
Offset: 0x24, reset: 0x00000000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IN2SEL
rw |
IN1SEL
rw |
||||||||||||||
Bits 0-1: LPTIM input 1 selection The IN1SEL bits control the LPTIM Input 1 multiplexer, which connects LPTIM Input 1 to one of the available inputs. For connection details refer to ..
Allowed values:
0x0: B_0x0: lptim_in1_mux0
0x1: B_0x1: lptim_in1_mux1
0x2: B_0x2: lptim_in1_mux2
0x3: B_0x3: lptim_in1_mux3
Bits 4-5: LPTIM input 2 selection The IN2SEL bits control the LPTIM Input 2 multiplexer, which connect LPTIM Input 2 to one of the available inputs. For connection details refer to . Note: If the LPTIM does not support encoder mode feature, these bits are reserved. Please refer to ..
Allowed values:
0x0: B_0x0: lptim_in2_mux0
0x1: B_0x1: lptim_in2_mux1
0x2: B_0x2: lptim_in2_mux2
0x3: B_0x3: lptim_in2_mux3
0x40008000: Low-power universal asynchronous receiver transmitter
96/120 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_disabled | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_enabled | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_disabled | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_enabled | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
LPUART control register 1 [alternate]
Offset: 0x0, reset: 0x00000000, access: Unspecified
15/19 fields covered.
Bit 0: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit..
Allowed values:
0x0: B_0x0: LPUART prescaler and outputs disabled, low-power mode
0x1: B_0x1: LPUART enabled
Bit 1: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode..
Allowed values:
0x0: B_0x0: LPUART not able to wake up the MCU from low-power mode.
0x1: B_0x1: LPUART able to wake up the MCU from low-power mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (â0â followed by â1â) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
LPUART control register 1 [alternate]
Offset: 0x0, reset: 0x00000000, access: Unspecified
17/21 fields covered.
Bit 0: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit..
Allowed values:
0x0: B_0x0: LPUART prescaler and outputs disabled, low-power mode
0x1: B_0x1: LPUART enabled
Bit 1: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode..
Allowed values:
0x0: B_0x0: LPUART not able to wake up the MCU from low-power mode.
0x1: B_0x1: LPUART able to wake up the MCU from low-power mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (â0â followed by â1â) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
LPUART control register 2
Offset: 0x4, reset: 0x00000000, access: Unspecified
7/8 fields covered.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD = 1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD = 0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD = 1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD = 0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bits 24-31: Address of the LPUART node ADD[7:4]: These bits give the address of the LPUART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or Stop mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UEÂ =Â 0) ADD[3:0]: These bits give the address of the LPUART node or a character code to be recognized. They are used for wakeup with address mark detection in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UEÂ =Â 0).
LPUART control register 3
Offset: 0x8, reset: 0x00000000, access: Unspecified
17/17 fields covered.
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 in the LPUART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated when FE = 1 or ORE = 1 or NE = 1 in the LPUART_ISR register.
Bit 8: RTS enable This bit can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the LPUART is disabled (UEÂ =Â 0).
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data..
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred.
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on Start bit detection
0x3: B_0x3: WUF active on RXNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An LPUART interrupt is generated whenever WUF = 1 in the LPUART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth.
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth.
0x6: B_0x6: Receive FIFO reaches 1/2 of its depth.
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth.
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth.
0x5: B_0x5: Receive FIFO becomes full.
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth.
0x1: B_0x1: TXFIFO reaches 1/4 of its depth.
0x6: B_0x6: TXFIFO reaches 1/2 of its depth.
0x3: B_0x3: TXFIFO reaches 3/4 of its depth.
0x4: B_0x4: TXFIFO reaches 7/8 of its depth.
0x5: B_0x5: TXFIFO becomes empty.
LPUART baud rate register
Offset: 0xc, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BRR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
LPUART request register
Offset: 0x18, reset: 0x00000000, access: Unspecified
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXFRQ
w |
RXFRQ
w |
MMRQ
w |
SBKRQ
w |
||||||||||||
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
LPUART interrupt and status register [alternate]
Offset: 0x1c, reset: 0x008000C0, access: Unspecified
17/17 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the LPUART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit  = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Data register is full/Transmit FIFO is full.
0x1: B_0x1: Data register/Transmit FIFO is not full.
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: LPUART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in LPUART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Receiver in Active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value.
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the LPUART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
LPUART interrupt and status register [alternate]
Offset: 0x1c, reset: 0x008000C0, access: Unspecified
21/21 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the LPUART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit  = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Data register is full/Transmit FIFO is full.
0x1: B_0x1: Data register/Transmit FIFO is not full.
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: LPUART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in LPUART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Receiver in Active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value.
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the LPUART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO is not empty
0x1: B_0x1: TXFIFO is empty
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO is not full
0x1: B_0x1: RXFIFO is full
Bit 26: RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
LPUART receive data register
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
LPUART transmit data register
Offset: 0x28, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Bits 0-8: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNFÂ =Â 1..
LPUART prescaler register
Offset: 0x2c, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40008400: Low-power universal asynchronous receiver transmitter
96/120 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_disabled | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_enabled | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_disabled | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_enabled | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
LPUART control register 1 [alternate]
Offset: 0x0, reset: 0x00000000, access: Unspecified
15/19 fields covered.
Bit 0: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit..
Allowed values:
0x0: B_0x0: LPUART prescaler and outputs disabled, low-power mode
0x1: B_0x1: LPUART enabled
Bit 1: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode..
Allowed values:
0x0: B_0x0: LPUART not able to wake up the MCU from low-power mode.
0x1: B_0x1: LPUART able to wake up the MCU from low-power mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (â0â followed by â1â) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
LPUART control register 1 [alternate]
Offset: 0x0, reset: 0x00000000, access: Unspecified
17/21 fields covered.
Bit 0: LPUART enable When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and current operations are discarded. The configuration of the LPUART is kept, but all the status flags, in the LPUART_ISR are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be reset before and the software must wait for the TC bit in the LPUART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit..
Allowed values:
0x0: B_0x0: LPUART prescaler and outputs disabled, low-power mode
0x1: B_0x1: LPUART enabled
Bit 1: LPUART enable in Stop mode When this bit is cleared, the LPUART is not able to wake up the MCU from low-power mode. When this bit is set, the LPUART is able to wake up the MCU from low-power mode, provided that the LPUART clock selection is HSI or LSE in the RCC. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it on exit from low-power mode..
Allowed values:
0x0: B_0x0: LPUART not able to wake up the MCU from low-power mode.
0x1: B_0x1: LPUART able to wake up the MCU from low-power mode. When this function is active, the clock source for the LPUART must be HSI or LSE (see RCC chapter)
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit (â0â followed by â1â) sends a preamble (idle line) after the current word. In order to generate an idle character, the TE must not be immediately written to 1. In order to ensure the required duration, the software can poll the TEACK bit in the LPUART_ISR register. When TE is set there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal.It is expressed in lpuart_ker_ck clock cycles. For more details, refer control and RS485 Driver Enable. If the LPUART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more details, refer . This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 Start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 Start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 Start bit, 7 Data bits, n Stop bit This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
LPUART control register 2
Offset: 0x4, reset: 0x00000000, access: Unspecified
7/8 fields covered.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the LPUART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD = 1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD = 0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD = 1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD = 0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bits 24-31: Address of the LPUART node ADD[7:4]: These bits give the address of the LPUART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or Stop mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UEÂ =Â 0) ADD[3:0]: These bits give the address of the LPUART node or a character code to be recognized. They are used for wakeup with address mark detection in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the LPUART is disabled (UEÂ =Â 0).
LPUART control register 3
Offset: 0x8, reset: 0x00000000, access: Unspecified
17/17 fields covered.
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 in the LPUART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated when FE = 1 or ORE = 1 or NE = 1 in the LPUART_ISR register.
Bit 8: RTS enable This bit can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the LPUART is disabled (UEÂ =Â 0).
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the LPUART_RDR register. This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data..
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the LPUART is disabled (UEÂ =Â 0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred.
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the LPUART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the LPUART is disabled (UEÂ =Â 0). Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on Start bit detection
0x3: B_0x3: WUF active on RXNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An LPUART interrupt is generated whenever WUF = 1 in the LPUART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth.
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth.
0x6: B_0x6: Receive FIFO reaches 1/2 of its depth.
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth.
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth.
0x5: B_0x5: Receive FIFO becomes full.
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved..
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth.
0x1: B_0x1: TXFIFO reaches 1/4 of its depth.
0x6: B_0x6: TXFIFO reaches 1/2 of its depth.
0x3: B_0x3: TXFIFO reaches 3/4 of its depth.
0x4: B_0x4: TXFIFO reaches 7/8 of its depth.
0x5: B_0x5: TXFIFO becomes empty.
LPUART baud rate register
Offset: 0xc, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BRR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
LPUART request register
Offset: 0x18, reset: 0x00000000, access: Unspecified
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXFRQ
w |
RXFRQ
w |
MMRQ
w |
SBKRQ
w |
||||||||||||
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: If the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request This bit is used when FIFO mode is enabled. TXFRQ bit is set to flush the whole FIFO. This sets the flag TXFE (TXFIFO empty, bit 23 in the LPUART_ISR register). Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
LPUART interrupt and status register [alternate]
Offset: 0x1c, reset: 0x008000C0, access: Unspecified
17/17 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the LPUART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit  = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Data register is full/Transmit FIFO is full.
0x1: B_0x1: Data register/Transmit FIFO is not full.
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: LPUART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in LPUART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Receiver in Active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value.
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the LPUART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
LPUART interrupt and status register [alternate]
Offset: 0x1c, reset: 0x008000C0, access: Unspecified
21/21 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the LPUART_ICR register. An interrupt is generated if PEIE = 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the LPUART_CR1 register. Note: This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Start bit noise detection flag This bit is set by hardware when noise is detected on the start bit of a received frame. It is cleared by software, writing 1 to the NECF bit in the LPUART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. This error is associated with the character in the LPUART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the LPUART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the LPUART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the LPUART_CR1 register. Note: When this bit is set, the LPUART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the LPUART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the LPUART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, and so data can be read from the LPUART_RDR register. Every read of the LPUART_RDR frees a location in the RXFIFO. It is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXFF is set. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the LPUART_TDR register. An interrupt is generated if TCIEÂ =Â 1 in the LPUART_CR1 register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full, and so data can be written in the LPUART_TDR. Every write in the LPUART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the LPUART_TDR. The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). An interrupt is generated if the TXFNFIE bit  = 1 in the LPUART_CR1 register. Note: This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Data register is full/Transmit FIFO is full.
0x1: B_0x1: Data register/Transmit FIFO is not full.
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the LPUART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the LPUART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: LPUART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the LPUART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in LPUART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the LPUART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the LPUART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the LPUART_RQR register. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Receiver in Active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the LPUART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value.
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the LPUART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the LPUART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the LPUART. It can be used to verify that the LPUART is ready for reception before entering low-power mode. Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the LPUART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO is not empty
0x1: B_0x1: TXFIFO is empty
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the LPUART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the LPUART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO is not full
0x1: B_0x1: RXFIFO is full
Bit 26: RXFIFO threshold flag This bit is set by hardware when the RXFIFO reaches the threshold programmed in RXFTCFG in LPUART_CR3 register i.e. the Receive FIFO contains RXFTCFG data. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG in LPUART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the LPUART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
LPUART receive data register
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
LPUART transmit data register
Offset: 0x28, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Bits 0-8: Transmit data value Contains the data character to be transmitted. The TDR register provides the parallel interface between the internal bus and the output shift register (see ). When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register), the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect because it is replaced by the parity. Note: This register must be written only when TXE/TXFNFÂ =Â 1..
LPUART prescaler register
Offset: 0x2c, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The LPUART input clock can be divided by a prescaler: Remaining combinations: Reserved. Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40007000: Power control
15/242 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | CR4 | ||||||||||||||||||||||||||||||||
| 0x10 | SR1 | ||||||||||||||||||||||||||||||||
| 0x14 | SR2 | ||||||||||||||||||||||||||||||||
| 0x18 | SCR | ||||||||||||||||||||||||||||||||
| 0x20 | PUCRA | ||||||||||||||||||||||||||||||||
| 0x24 | PDCRA | ||||||||||||||||||||||||||||||||
| 0x28 | PUCRB | ||||||||||||||||||||||||||||||||
| 0x2c | PDCRB | ||||||||||||||||||||||||||||||||
| 0x30 | PUCRC | ||||||||||||||||||||||||||||||||
| 0x34 | PDCRC | ||||||||||||||||||||||||||||||||
| 0x38 | PUCRD | ||||||||||||||||||||||||||||||||
| 0x3c | PDCRD | ||||||||||||||||||||||||||||||||
| 0x40 | PUCRE | ||||||||||||||||||||||||||||||||
| 0x44 | PDCRE | ||||||||||||||||||||||||||||||||
| 0x48 | PUCRF | ||||||||||||||||||||||||||||||||
| 0x4c | PDCRF | ||||||||||||||||||||||||||||||||
0x40021000: Reset and clock control
24/237 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | ICSCR | ||||||||||||||||||||||||||||||||
| 0x8 | CFGR | ||||||||||||||||||||||||||||||||
| 0xc | PLLCFGR | ||||||||||||||||||||||||||||||||
| 0x14 | CRRCR | ||||||||||||||||||||||||||||||||
| 0x18 | CIER | ||||||||||||||||||||||||||||||||
| 0x1c | CIFR | ||||||||||||||||||||||||||||||||
| 0x20 | CICR | ||||||||||||||||||||||||||||||||
| 0x24 | IOPRSTR | ||||||||||||||||||||||||||||||||
| 0x28 | AHBRSTR | ||||||||||||||||||||||||||||||||
| 0x2c | APBRSTR1 | ||||||||||||||||||||||||||||||||
| 0x30 | APBRSTR2 | ||||||||||||||||||||||||||||||||
| 0x34 | IOPENR | ||||||||||||||||||||||||||||||||
| 0x38 | AHBENR | ||||||||||||||||||||||||||||||||
| 0x3c | APBENR1 | ||||||||||||||||||||||||||||||||
| 0x40 | APBENR2 | ||||||||||||||||||||||||||||||||
| 0x44 | IOPSMENR | ||||||||||||||||||||||||||||||||
| 0x48 | AHBSMENR | ||||||||||||||||||||||||||||||||
| 0x4c | APBSMENR1 | ||||||||||||||||||||||||||||||||
| 0x50 | APBSMENR2 | ||||||||||||||||||||||||||||||||
| 0x54 | CCIPR | ||||||||||||||||||||||||||||||||
| 0x58 | CCIPR2 | ||||||||||||||||||||||||||||||||
| 0x5c | BDCR | ||||||||||||||||||||||||||||||||
| 0x60 | CSR | ||||||||||||||||||||||||||||||||
Internal clock sources calibration register
Offset: 0x4, reset: 0x00004000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HSITRIM
rw |
HSICAL
r |
||||||||||||||
RCC clock recovery RC register
Offset: 0x14, reset: 0x00000000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
HSI48CAL
r |
|||||||||||||||
Clock interrupt enable register
Offset: 0x18, reset: 0x00000000, access: read-write
0/5 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PLLSYSRDYIE
rw |
HSERDYIE
rw |
HSIRDYIE
rw |
LSERDYIE
rw |
LSIRDYIE
rw |
|||||||||||
Clock interrupt flag register
Offset: 0x1c, reset: 0x00000000, access: read-only
8/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LSECSSF
r |
CSSF
r |
PLLSYSRDYF
r |
HSERDYF
r |
HSIRDYF
r |
HSI48RDYF
r |
LSERDYF
r |
LSIRDYF
r |
||||||||
Clock interrupt clear register
Offset: 0x20, reset: 0x00000000, access: write-only
0/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
LSECSSC
w |
CSSC
w |
PLLSYSRDYC
w |
HSERDYC
w |
HSIRDYC
w |
HSI48RDYC
w |
LSERDYC
w |
LSIRDYC
w |
||||||||
AHB peripheral reset register
Offset: 0x28, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCRST
rw |
FLASHRST
rw |
DMA2RST
rw |
DMA1RST
rw |
||||||||||||
APB peripheral reset register 1
Offset: 0x2c, reset: 0x00000000, access: read-write
0/28 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LPTIM1RST
rw |
LPTIM2RST
rw |
DAC1RST
rw |
PWRRST
rw |
DBGRST
rw |
UCPD2RST
rw |
UCPD1RST
rw |
CECRST
rw |
I2C3RST
rw |
I2C2RST
rw |
I2C1RST
rw |
LPUART1RST
rw |
USART4RST
rw |
USART3RST
rw |
USART2RST
rw |
CRSRST
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3RST
rw |
SPI2RST
rw |
USBRST
rw |
FDCANRST
rw |
USART6RST
rw |
USART5RST
rw |
LPUART2RST
rw |
TIM7RST
rw |
TIM6RST
rw |
TIM4RST
rw |
TIM3RST
rw |
TIM2RST
rw |
||||
AHB peripheral clock enable register
Offset: 0x38, reset: 0x00000100, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCEN
rw |
FLASHEN
rw |
DMA2EN
rw |
DMA1EN
rw |
||||||||||||
APB peripheral clock enable register 1
Offset: 0x3c, reset: 0x00000000, access: read-write
0/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LPTIM1EN
rw |
LPTIM2EN
rw |
DAC1EN
rw |
PWREN
rw |
DBGEN
rw |
UCPD2EN
rw |
UCPD1EN
rw |
CECEN
rw |
I2C3EN
rw |
I2C2EN
rw |
I2C1EN
rw |
LPUART1EN
rw |
USART4EN
rw |
USART3EN
rw |
USART2EN
rw |
CRSEN
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3EN
rw |
SPI2EN
rw |
USBEN
rw |
FDCANEN
rw |
WWDGEN
rw |
RTCAPBEN
rw |
USART6EN
rw |
USART5EN
rw |
LPUART2EN
rw |
TIM7EN
rw |
TIM6EN
rw |
TIM4EN
rw |
TIM3EN
rw |
TIM2EN
rw |
APB peripheral clock enable in Sleep mode register 1
Offset: 0x4c, reset: 0xFFFFFFB7, access: read-write
0/30 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
LPTIM1SMEN
rw |
LPTIM2SMEN
rw |
DAC1SMEN
rw |
PWRSMEN
rw |
DBGSMEN
rw |
UCPD2SMEN
rw |
UCPD1SMEN
rw |
CECSMEN
rw |
I2C3SMEN
rw |
I2C2SMEN
rw |
I2C1SMEN
rw |
LPUART1SMEN
rw |
USART4SMEN
rw |
USART3SMEN
rw |
USART2SMEN
rw |
CRSSSMEN
rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SPI3SMEN
rw |
SPI2SMEN
rw |
USBSMEN
rw |
FDCANSMEN
rw |
WWDGSMEN
rw |
RTCAPBSMEN
rw |
USART6SMEN
rw |
USART5SMEN
rw |
LPUART2SMEN
rw |
TIM7SMEN
rw |
TIM6SMEN
rw |
TIM4SMEN
rw |
TIM3SMEN
rw |
TIM2SMEN
rw |
APB peripheral clock enable in Sleep mode register 2
Offset: 0x50, reset: 0x0017D801, access: read-write
0/9 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADCSMEN
rw |
TIM17SMEN
rw |
TIM16SMEN
rw |
TIM15SMEN
rw |
||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TIM14SMEN
rw |
USART1SMEN
rw |
SPI1SMEN
rw |
TIM1SMEN
rw |
SYSCFGSMEN
rw |
|||||||||||
Peripherals independent clock configuration register
Offset: 0x54, reset: 0x00000000, access: read-write
0/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADCSEL
rw |
TIM15SEL
rw |
TIM1SEL
rw |
LPTIM2SEL
rw |
LPTIM1SEL
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
I2S2SEL
rw |
I2C1SEL
rw |
LPUART1SEL
rw |
LPUART2SEL
rw |
CECSEL
rw |
USART3SEL
rw |
USART2SEL
rw |
USART1SEL
rw |
||||||||
Peripherals independent clock configuration register 2
Offset: 0x58, reset: 0x00000000, access: read-write
0/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
USBSEL
rw |
FDCANSEL
rw |
I2S2SEL
rw |
I2S1SEL
rw |
||||||||||||
0x40002800: Real-time clock
77/123 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | TR | ||||||||||||||||||||||||||||||||
| 0x4 | DR | ||||||||||||||||||||||||||||||||
| 0x8 | SSR | ||||||||||||||||||||||||||||||||
| 0xc | ICSR | ||||||||||||||||||||||||||||||||
| 0x10 | PRER | ||||||||||||||||||||||||||||||||
| 0x14 | WUTR | ||||||||||||||||||||||||||||||||
| 0x18 | CR | ||||||||||||||||||||||||||||||||
| 0x24 | WPR | ||||||||||||||||||||||||||||||||
| 0x28 | CALR | ||||||||||||||||||||||||||||||||
| 0x2c | SHIFTR | ||||||||||||||||||||||||||||||||
| 0x30 | TSTR | ||||||||||||||||||||||||||||||||
| 0x34 | TSDR | ||||||||||||||||||||||||||||||||
| 0x38 | TSSSR | ||||||||||||||||||||||||||||||||
| 0x40 | ALRMAR | ||||||||||||||||||||||||||||||||
| 0x44 | ALRMASSR | ||||||||||||||||||||||||||||||||
| 0x48 | ALRMBR | ||||||||||||||||||||||||||||||||
| 0x4c | ALRMBSSR | ||||||||||||||||||||||||||||||||
| 0x50 | SR | ||||||||||||||||||||||||||||||||
| 0x54 | MISR | ||||||||||||||||||||||||||||||||
| 0x5c | SCR | ||||||||||||||||||||||||||||||||
RTC sub second register
Offset: 0x8, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
Bits 0-15: Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR..
RTC initialization control and status register
Offset: 0xc, reset: 0x00000007, access: Unspecified
9/9 fields covered.
Bit 2: Wakeup timer write flag This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode..
Allowed values:
0x0: B_0x0: Wakeup timer configuration update not allowed except in initialization mode
0x1: B_0x1: Wakeup timer configuration update allowed
Bit 3: Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect..
Allowed values:
0x0: B_0x0: No shift operation is pending
0x1: B_0x1: A shift operation is pending
Bit 5: Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode..
Allowed values:
0x0: B_0x0: Calendar shadow registers not yet synchronized
0x1: B_0x1: Calendar shadow registers synchronized
RTC prescaler register
Offset: 0x10, reset: 0x007F00FF, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
PREDIV_A
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PREDIV_S
rw |
|||||||||||||||
RTC wakeup timer register
Offset: 0x14, reset: 0x0000FFFF, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUT
rw |
|||||||||||||||
Bits 0-15: Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]Â +Â 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register. When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs between WUT and (WUT + 1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden..
RTC control register
Offset: 0x18, reset: 0x00000000, access: Unspecified
24/26 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
OUT2EN
rw |
TAMPALRM_TYPE
rw |
TAMPALRM_PU
rw |
TAMPOE
rw |
TAMPTS
rw |
ITSE
rw |
COE
rw |
OSEL
rw |
POL
rw |
COSEL
rw |
BKP
rw |
SUB1H
w |
ADD1H
w |
|||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TSIE
rw |
WUTIE
rw |
ALRBIE
rw |
ALRAIE
rw |
TSE
rw |
WUTE
rw |
ALRBE
rw |
ALRAE
rw |
FMT
rw |
BYPSHAD
rw |
REFCKON
rw |
TSEDGE
rw |
WUCKSEL
rw |
|||
Bits 0-2: ck_wut wakeup clock selection 10x: ck_spre (usually 1Â Hz) clock is selected 11x: ck_spre (usually 1Â Hz) clock is selected and 216Â is added to the WUT counter value.
Allowed values:
0x0: B_0x0: RTC/16 clock is selected
0x1: B_0x1: RTC/8 clock is selected
0x2: B_0x2: RTC/4 clock is selected
0x3: B_0x3: RTC/2 clock is selected
Bit 5: Bypass the shadow registers Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1..
Allowed values:
0x0: B_0x0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles.
0x1: B_0x1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters.
Bit 17: Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0..
Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Subtracts 1 hour to the current time. This can be used for winter time change.
Bit 19: Calibration output selection When COE = 1, this bit selects which signal is output on CALIB. These frequencies are valid for RTCCLK at 32.768Â kHz and prescalers at their default values (PREDIV_A = 127 and PREDIV_S = 255). Refer to ..
Allowed values:
0x0: B_0x0: Calibration output is 512 Hz
0x1: B_0x1: Calibration output is 1 Hz
Bit 20: Output polarity This bit is used to configure the polarity of TAMPALRM output..
Allowed values:
0x0: B_0x0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).
0x1: B_0x1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]), or when a TAMPxF/ITAMPxF is asserted (if TAMPOE = 1).
Bit 25: Activate timestamp on tamper detection event TAMPTS is valid even if TSE = 0 in the RTC_CR register. Timestamp flag is set after the tamper flags, therefore if TAMPTS and TSIE are set, it is recommended to disable the tamper interrupts in order to avoid servicing 2 interrupts..
Allowed values:
0x0: B_0x0: Tamper detection event does not cause a RTC timestamp to be saved
0x1: B_0x1: Save RTC timestamp on tamper detection event
Bit 31: RTC_OUT2 output enable Setting this bit allows to remap the RTC outputs on RTC_OUT2 as follows: OUT2EN = 0: RTC output 2 disable If OSEL â 00 or TAMPOE = 1: TAMPALRM is output on RTC_OUT1 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT1 OUT2EN = 1: RTC output 2 enable If (OSEL â 00 or TAMPOE = 1) and COE = 0: TAMPALRM is output on RTC_OUT2 If OSEL = 00 and TAMPOE = 0 and COE = 1: CALIB is output on RTC_OUT2 If (OSELâ 00 or TAMPOE = 1) and COE = 1: CALIB is output on RTC_OUT2 and TAMPALRM is output on RTC_OUT1..
RTC write protection register
Offset: 0x24, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
KEY
w |
|||||||||||||||
RTC calibration register
Offset: 0x28, reset: 0x00000000, access: Unspecified
1/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CALP
rw |
CALW8
rw |
CALW16
rw |
CALM
rw |
||||||||||||
Bits 0-8: Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768Â Hz). This decreases the frequency of the calendar with a resolution of 0.9537Â ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See ..
Bit 15: Increase frequency of RTC by 488.5Â ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768Â Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 Ã CALP) - CALM. Refer to ..
Allowed values:
0x0: B_0x0: No RTCCLK pulses are added.
0x1: B_0x1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5Â ppm).
RTC shift control register
Offset: 0x2c, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ADD1S
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SUBFS
w |
|||||||||||||||
Bits 0-14: Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF = 1 to be sure that the shadow registers have been updated with the shifted time..
Bit 31: Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF = 1, in RTC_ICSR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation..
Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Add one second to the clock/calendar
RTC timestamp sub second register
Offset: 0x38, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
r |
|||||||||||||||
RTC alarm A sub second register
Offset: 0x44, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
Bits 24-27: Mask the most-significant bits starting at this bit 2: SS[14:2] are don't care in alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are don't care in alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are don't care in alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are don't care in alarm A comparison. SS[12:0] are compared. 14: SS[14] is don't care in alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm. The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation. Note: The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..
Allowed values:
0x0: B_0x0: No comparison on sub seconds for alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
0x1: B_0x1: SS[14:1] are don't care in alarm A comparison. Only SS[0] is compared.
RTC alarm B sub second register
Offset: 0x4c, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
MASKSS
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
SS
rw |
|||||||||||||||
Bits 24-27: Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation..
Allowed values:
0x0: B_0x0: No comparison on sub seconds for alarm B. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match).
0x1: B_0x1: SS[14:1] are don't care in alarm B comparison. Only SS[0] is compared.
0x2: B_0x2: SS[14:2] are don't care in alarm B comparison. Only SS[1:0] are compared.
0x3: B_0x3: SS[14:3] are don't care in alarm B comparison. Only SS[2:0] are compared.
0xC: B_0xC: SS[14:12] are don't care in alarm B comparison. SS[11:0] are compared.
0xD: B_0xD: SS[14:13] are don't care in alarm B comparison. SS[12:0] are compared.
0xE: B_0xE: SS[14] is don't care in alarm B comparison. SS[13:0] are compared.
0xF: B_0xF: All 15 SS bits are compared and must match to activate alarm.
RTC status register
Offset: 0x50, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 4: Timestamp overflow flag This flag is set by hardware when a timestamp event occurs while TSF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..
RTC masked interrupt status register
Offset: 0x54, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 4: Timestamp overflow masked flag This flag is set by hardware when a timestamp interrupt occurs while TSMF is already set. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..
RTC status clear register
Offset: 0x5c, reset: 0x00000000, access: Unspecified
0/6 fields covered.
Bit 4: Clear timestamp overflow flag Writing 1 in this bit clears the TSOVF bit in the RTC_SR register. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared..
0x40013000: Serial peripheral interface
49/53 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
SPI control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
13/14 fields covered.
Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: fPCLK/2
0x1: B_0x1: fPCLK/4
0x2: B_0x2: fPCLK/8
0x3: B_0x3: fPCLK/16
0x4: B_0x4: fPCLK/32
0x5: B_0x5: fPCLK/64
0x6: B_0x6: fPCLK/128
0x7: B_0x7: fPCLK/256
Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Full-duplex (Transmit and receive)
0x1: B_0x1: Output disabled (Receive-only mode)
Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Output disabled (receive-only mode)
0x1: B_0x1: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: 2-line unidirectional data mode selected
0x1: B_0x1: 1-line bidirectional data mode selected
SPI control register 2
Offset: 0x4, reset: 0x00000700, access: Unspecified
12/12 fields covered.
Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration
0x1: B_0x1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.
Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = â1â, or FRF = â1â. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: No NSS pulse
0x1: B_0x1: NSS pulse generated
Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the âNot usedâ values, they are forced to the value â0111â (8-bit) Note: These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: Not used
0x1: B_0x1: Not used
0x2: B_0x2: Not used
0x3: B_0x3: 4-bit
0x4: B_0x4: 5-bit
0x5: B_0x5: 6-bit
0x6: B_0x6: 7-bit
0x7: B_0x7: 8-bit
0x8: B_0x8: 9-bit
0x9: B_0x9: 10-bit
0xA: B_0xA: 11-bit
0xB: B_0xB: 12-bit
0xC: B_0xC: 13-bit
0xD: B_0xD: 14-bit
0xE: B_0xE: 15-bit
0xF: B_0xF: 16-bit
Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
0x1: B_0x1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
SPI data register
Offset: 0xc, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..
SPI CRC polynomial register
Offset: 0x10, reset: 0x00000007, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
SPI Rx CRC register
Offset: 0x14, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXCRC
r |
|||||||||||||||
Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI Tx CRC register
Offset: 0x18, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXCRC
r |
|||||||||||||||
Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI_I2S configuration register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
9/9 fields covered.
Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: 16-bit wide
0x1: B_0x1: 32-bit wide
Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..
Allowed values:
0x0: B_0x0: I2S clock inactive state is low level
0x1: B_0x1: I2S clock inactive state is high level
Bits 4-5: I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode..
Allowed values:
0x0: B_0x0: I2S Philips standard
0x1: B_0x1: MSB justified standard (left justified)
0x2: B_0x2: LSB justified standard (right justified)
0x3: B_0x3: PCM standard
Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information..
Allowed values:
0x0: B_0x0: The Asynchronous start is disabled.
0x1: B_0x1: The Asynchronous start is enabled.
SPI_I2S prescaler register
Offset: 0x20, reset: 0x00000002, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
Bit 8: Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: Real divider value is = I2SDIV *2
0x1: B_0x1: Real divider value is = (I2SDIV * 2) + 1
0x40003800: Serial peripheral interface
49/53 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
SPI control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
13/14 fields covered.
Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: fPCLK/2
0x1: B_0x1: fPCLK/4
0x2: B_0x2: fPCLK/8
0x3: B_0x3: fPCLK/16
0x4: B_0x4: fPCLK/32
0x5: B_0x5: fPCLK/64
0x6: B_0x6: fPCLK/128
0x7: B_0x7: fPCLK/256
Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Full-duplex (Transmit and receive)
0x1: B_0x1: Output disabled (Receive-only mode)
Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Output disabled (receive-only mode)
0x1: B_0x1: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: 2-line unidirectional data mode selected
0x1: B_0x1: 1-line bidirectional data mode selected
SPI control register 2
Offset: 0x4, reset: 0x00000700, access: Unspecified
12/12 fields covered.
Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration
0x1: B_0x1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.
Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = â1â, or FRF = â1â. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: No NSS pulse
0x1: B_0x1: NSS pulse generated
Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the âNot usedâ values, they are forced to the value â0111â (8-bit) Note: These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: Not used
0x1: B_0x1: Not used
0x2: B_0x2: Not used
0x3: B_0x3: 4-bit
0x4: B_0x4: 5-bit
0x5: B_0x5: 6-bit
0x6: B_0x6: 7-bit
0x7: B_0x7: 8-bit
0x8: B_0x8: 9-bit
0x9: B_0x9: 10-bit
0xA: B_0xA: 11-bit
0xB: B_0xB: 12-bit
0xC: B_0xC: 13-bit
0xD: B_0xD: 14-bit
0xE: B_0xE: 15-bit
0xF: B_0xF: 16-bit
Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
0x1: B_0x1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
SPI data register
Offset: 0xc, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..
SPI CRC polynomial register
Offset: 0x10, reset: 0x00000007, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
SPI Rx CRC register
Offset: 0x14, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXCRC
r |
|||||||||||||||
Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI Tx CRC register
Offset: 0x18, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXCRC
r |
|||||||||||||||
Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI_I2S configuration register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
9/9 fields covered.
Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: 16-bit wide
0x1: B_0x1: 32-bit wide
Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..
Allowed values:
0x0: B_0x0: I2S clock inactive state is low level
0x1: B_0x1: I2S clock inactive state is high level
Bits 4-5: I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode..
Allowed values:
0x0: B_0x0: I2S Philips standard
0x1: B_0x1: MSB justified standard (left justified)
0x2: B_0x2: LSB justified standard (right justified)
0x3: B_0x3: PCM standard
Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information..
Allowed values:
0x0: B_0x0: The Asynchronous start is disabled.
0x1: B_0x1: The Asynchronous start is enabled.
SPI_I2S prescaler register
Offset: 0x20, reset: 0x00000002, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
Bit 8: Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: Real divider value is = I2SDIV *2
0x1: B_0x1: Real divider value is = (I2SDIV * 2) + 1
0x40003c00: Serial peripheral interface
49/53 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
| 0xc | DR | ||||||||||||||||||||||||||||||||
| 0x10 | CRCPR | ||||||||||||||||||||||||||||||||
| 0x14 | RXCRCR | ||||||||||||||||||||||||||||||||
| 0x18 | TXCRCR | ||||||||||||||||||||||||||||||||
| 0x1c | I2SCFGR | ||||||||||||||||||||||||||||||||
| 0x20 | I2SPR | ||||||||||||||||||||||||||||||||
SPI control register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
13/14 fields covered.
Bit 0: Clock phase Note: This bit should not be changed when communication is ongoing. This bit is not used in I2S mode and SPI TI mode except the case when CRC is applied at TI mode..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bits 3-5: Baud rate control Note: These bits should not be changed when communication is ongoing. These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: fPCLK/2
0x1: B_0x1: fPCLK/4
0x2: B_0x2: fPCLK/8
0x3: B_0x3: fPCLK/16
0x4: B_0x4: fPCLK/32
0x5: B_0x5: fPCLK/64
0x6: B_0x6: fPCLK/128
0x7: B_0x7: fPCLK/256
Bit 10: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Full-duplex (Transmit and receive)
0x1: B_0x1: Output disabled (Receive-only mode)
Bit 14: Output enable in bidirectional mode This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional mode. Note: In master mode, the MOSI pin is used and in slave mode, the MISO pin is used. This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: Output disabled (receive-only mode)
0x1: B_0x1: Output enabled (transmit-only mode)
Bit 15: Bidirectional data mode enable. This bit enables half-duplex communication using common single bidirectional data line. Keep RXONLY bit clear when bidirectional mode is active. Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: 2-line unidirectional data mode selected
0x1: B_0x1: 1-line bidirectional data mode selected
SPI control register 2
Offset: 0x4, reset: 0x00000700, access: Unspecified
12/12 fields covered.
Bit 2: SS output enable Note: This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration
0x1: B_0x1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.
Bit 3: NSS pulse management This bit is used in master mode only. it allows the SPI to generate an NSS pulse between two consecutive data when doing continuous transfers. In the case of a single data transfer, it forces the NSS pin high level after the transfer. It has no meaning if CPHA = â1â, or FRF = â1â. Note: 1. This bit must be written only when the SPI is disabled (SPE=0). 2. This bit is not used in I2S mode and SPI TI mode..
Allowed values:
0x0: B_0x0: No NSS pulse
0x1: B_0x1: NSS pulse generated
Bits 8-11: Data size These bits configure the data length for SPI transfers. If software attempts to write one of the âNot usedâ values, they are forced to the value â0111â (8-bit) Note: These bits are not used in I2S mode..
Allowed values:
0x0: B_0x0: Not used
0x1: B_0x1: Not used
0x2: B_0x2: Not used
0x3: B_0x3: 4-bit
0x4: B_0x4: 5-bit
0x5: B_0x5: 6-bit
0x6: B_0x6: 7-bit
0x7: B_0x7: 8-bit
0x8: B_0x8: 9-bit
0x9: B_0x9: 10-bit
0xA: B_0xA: 11-bit
0xB: B_0xB: 12-bit
0xC: B_0xC: 13-bit
0xD: B_0xD: 14-bit
0xE: B_0xE: 15-bit
0xF: B_0xF: 16-bit
Bit 12: FIFO reception threshold This bit is used to set the threshold of the RXFIFO that triggers an RXNE event Note: This bit is not used in I2S mode..
Allowed values:
0x0: B_0x0: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
0x1: B_0x1: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
Bit 13: Last DMA transfer for reception This bit is used in data packing mode, to define if the total number of data to receive by DMA is odd or even. It has significance only if the RXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
Bit 14: Last DMA transfer for transmission This bit is used in data packing mode, to define if the total number of data to transmit by DMA is odd or even. It has significance only if the TXDMAEN bit in the SPI_CR2 register is set and if packing mode is used (data length =< 8-bit and write access to SPI_DR is 16-bit wide). It has to be written when the SPI is disabled (SPE = 0 in the SPI_CR1 register). Note: Refer to if the CRCEN bit is set. This bit is not used in I²S mode..
Allowed values:
0x0: B_0x0: Number of data to transfer is even
0x1: B_0x1: Number of data to transfer is odd
SPI data register
Offset: 0xc, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DR
rw |
|||||||||||||||
Bits 0-15: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See ). Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and read as zero when the register is read. The Rx threshold setting must always correspond with the read access currently used..
SPI CRC polynomial register
Offset: 0x10, reset: 0x00000007, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CRCPOLY
rw |
|||||||||||||||
SPI Rx CRC register
Offset: 0x14, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXCRC
r |
|||||||||||||||
Bits 0-15: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI Tx CRC register
Offset: 0x18, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXCRC
r |
|||||||||||||||
Bits 0-15: Tx CRC register When CRC calculation is enabled, the TXCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the CRC frame format is set to be 8-bit length (CRCL bit in the SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit CRC frame format is selected (CRCL bit in the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. These bits are not used in I2S mode..
SPI_I2S configuration register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
9/9 fields covered.
Bit 0: Channel length (number of bits per audio channel) The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: 16-bit wide
0x1: B_0x1: 32-bit wide
Bit 3: Inactive state clock polarity Note: For correct operation, this bit should be configured when the I2S is disabled. It is not used in SPI mode. The bit CKPOL does not affect the CK edge sensitivity used to receive or transmit the SD and WS signals..
Allowed values:
0x0: B_0x0: I2S clock inactive state is low level
0x1: B_0x1: I2S clock inactive state is high level
Bits 4-5: I2S standard selection For more details on I2S standards, refer to Note: For correct operation, these bits should be configured when the I2S is disabled. They are not used in SPI mode..
Allowed values:
0x0: B_0x0: I2S Philips standard
0x1: B_0x1: MSB justified standard (left justified)
0x2: B_0x2: LSB justified standard (right justified)
0x3: B_0x3: PCM standard
Bit 12: Asynchronous start enable. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and an appropriate transition is detected on the WS signal. When the I2S is enabled in slave mode, the hardware starts the transfer when the I2S clock is received and the appropriate level is detected on the WS signal. Note: The appropriate transition is a falling edge on WS signal when I2S Philips Standard is used, or a rising edge for other standards. The appropriate level is a low level on WS signal when I2S Philips Standard is used, or a high level for other standards. Please refer to for additional information..
Allowed values:
0x0: B_0x0: The Asynchronous start is disabled.
0x1: B_0x1: The Asynchronous start is enabled.
SPI_I2S prescaler register
Offset: 0x20, reset: 0x00000002, access: Unspecified
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MCKOE
rw |
ODD
rw |
I2SDIV
rw |
|||||||||||||
Bit 8: Odd factor for the prescaler Refer to . Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. It is not used in SPI mode..
Allowed values:
0x0: B_0x0: Real divider value is = I2SDIV *2
0x1: B_0x1: Real divider value is = (I2SDIV * 2) + 1
0x4000b000: Tamper and backup registers
34/45 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | FLTCR | ||||||||||||||||||||||||||||||||
| 0x2c | IER | ||||||||||||||||||||||||||||||||
| 0x30 | SR | ||||||||||||||||||||||||||||||||
| 0x34 | MISR | ||||||||||||||||||||||||||||||||
| 0x3c | SCR | ||||||||||||||||||||||||||||||||
| 0x100 | BKP0R | ||||||||||||||||||||||||||||||||
| 0x104 | BKP1R | ||||||||||||||||||||||||||||||||
| 0x108 | BKP2R | ||||||||||||||||||||||||||||||||
| 0x10c | BKP3R | ||||||||||||||||||||||||||||||||
| 0x110 | BKP4R | ||||||||||||||||||||||||||||||||
TAMP control register 1
Offset: 0x0, reset: 0xFFFF0000, access: Unspecified
6/6 fields covered.
Bit 20: Internal tamper 5 enable: RTC calendar overflow.
Allowed values:
0x0: B_0x0: Internal tamper 5 disabled.
0x1: B_0x1: Internal tamper 5 enabled: a tamper is generated when the RTC calendar reaches its maximum value, on the 31st of December 99, at 23:59:59. The calendar is then frozen and cannot overflow.
TAMP control register 2
Offset: 0x4, reset: 0x00000000, access: Unspecified
6/6 fields covered.
Bit 16: Tamper 1 mask The tamper 1 interrupt must not be enabled when TAMP1MSK is set..
Allowed values:
0x0: B_0x0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to allow next tamper event detection.
0x1: B_0x1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased.
Bit 17: Tamper 2 mask The tamper 2 interrupt must not be enabled when TAMP2MSK is set..
Allowed values:
0x0: B_0x0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to allow next tamper event detection.
0x1: B_0x1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased.
Bit 24: Active level for tamper 1 input (active mode disabled) If TAMPFLT = 00 Tamper 1 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 1 input falling edge and low level triggers a tamper detection event..
Allowed values:
0x0: B_0x0: If TAMPFLT â 00 Tamper 1 input staying low triggers a tamper detection event.
0x1: B_0x1: If TAMPFLT â 00 Tamper 1 input staying high triggers a tamper detection event.
Bit 25: Active level for tamper 2 input (active mode disabled) If TAMPFLT = 00 Tamper 2 input rising edge and high level triggers a tamper detection event. If TAMPFLT = 00 Tamper 2 input falling edge and low level triggers a tamper detection event..
Allowed values:
0x0: B_0x0: If TAMPFLT â 00 Tamper 2 input staying low triggers a tamper detection event.
0x1: B_0x1: If TAMPFLT â 00 Tamper 2 input staying high triggers a tamper detection event.
TAMP filter control register
Offset: 0xc, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TAMPPUDIS
rw |
TAMPPRCH
rw |
TAMPFLT
rw |
TAMPFREQ
rw |
||||||||||||
Bits 0-2: Tamper sampling frequency Determines the frequency at which each of the TAMP_INx inputs are sampled..
Allowed values:
0x0: B_0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: B_0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: B_0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: B_0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: B_0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: B_0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: B_0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: B_0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bits 3-4: TAMP_INx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the TAMP_INx inputs..
Allowed values:
0x0: B_0x0: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input).
0x1: B_0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: B_0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: B_0x3: Tamper event is activated after 8 consecutive samples at the active level.
Bits 5-6: TAMP_INx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the TAMP_INx inputs..
Allowed values:
0x0: B_0x0: 1 RTCCLK cycle
0x1: B_0x1: 2 RTCCLK cycles
0x2: B_0x2: 4 RTCCLK cycles
0x3: B_0x3: 8 RTCCLK cycles
TAMP backup 0 register
Offset: 0x100, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..
TAMP backup 1 register
Offset: 0x104, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..
TAMP backup 2 register
Offset: 0x108, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..
TAMP backup 3 register
Offset: 0x10c, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..
TAMP backup 4 register
Offset: 0x110, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BKP
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BKP
rw |
|||||||||||||||
Bits 0-31: The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. In the default configuration this register is reset on a tamper detection event. It is forced to reset value as long as there is at least one internal or external tamper flag being set. This register is also reset when the readout protection (RDP) is disabled..
0x40012c00: Advanced-timers
117/190 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x38 | CCR2 | ||||||||||||||||||||||||||||||||
| 0x3c | CCR3 | ||||||||||||||||||||||||||||||||
| 0x40 | CCR4 | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR1 | ||||||||||||||||||||||||||||||||
| 0x54 | CCMR3_Output | ||||||||||||||||||||||||||||||||
| 0x58 | CCR5 | ||||||||||||||||||||||||||||||||
| 0x5c | CCR6 | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x64 | AF2 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x00000000, access: read-write
9/9 fields covered.
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 5-6: Center-aligned mode selection Note: Switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) is not allowed.
Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx): Note: tDTS = 1/fDTS, tCK_INT = 1/fCK_INT..
Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value
control register 2
Offset: 0x4, reset: 0x00000000, access: read-write
8/15 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI
Bits 4-6: Master mode selection These bits allow selected information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Bits 20-23: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO2)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO2)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO2)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO2)
0x8: B_0x8: Compare - OC5REFC signal is used as trigger output (TRGO2)
0x9: B_0x9: Compare - OC6REFC signal is used as trigger output (TRGO2)
0xA: B_0xA: Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2
0xB: B_0xB: Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2
0xC: B_0xC: Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2
0xD: B_0xD: Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2
0xE: B_0xE: Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2
0xF: B_0xF: Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2
slave mode control register
Offset: 0x8, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/slave mode.
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of fCK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
status register
Offset: 0x10, reset: 0x0000, access: read-write
8/16 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM1_SMCRTIMx_SMCR)N/A), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred.
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.
Bit 7: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active..
Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
Bit 8: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active..
Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bit 13: System Break interrupt flag This flag is set by hardware as soon as the system break input goes active. It can be cleared by software if the system break input is not active. This flag must be reset to re-start PWM operation..
Allowed values:
0x0: B_0x0: No break event occurred.
0x1: B_0x1: An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register.
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
6/9 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. The prescaler internal counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware Note: This bit acts only on channels having a complementary output..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated.
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..
Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events
Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
8/12 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..
Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Bits 12-14: Output Compare 2 mode Refer to OC1M[3:0] description..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. Note: The OC1M[3] bit is not contiguous, located in bit 16..
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
2/6 fields covered.
Bits 0-1: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
6/12 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 4-6: Output compare 3 mode Refer to OC1M[3:0] description..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 12-14: Output compare 4 mode Refer to OC3M[3:0] description..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
4/19 fields covered.
Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details. Note: On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1E active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin
Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: The configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
Bit 2: Capture/Compare 1 complementary output enable On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NE active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (channel configured as output). On channels having a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1N active high.
0x1: B_0x1: OC1N active low.
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
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prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
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Bits 0-15: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in âreset modeâ)..
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
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repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
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capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
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capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
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capture/compare register 3
Offset: 0x3c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR3
rw |
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capture/compare register 4
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR4
rw |
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break and dead-time register
Offset: 0x44, reset: 0x0000, access: read-write
13/16 fields covered.
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tDTG with tDTG=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtDTG with tDTG=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtDTG with tDTG=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtDTG with tDTG=16xtDTS. Example if tDTS=125 ns (8 MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 μs to 31750 ns by 250 ns steps, 32 μs to 63 μs by 1 μs steps, 64 μs to 126 μs by 2 μs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected.
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BK2BID, BKBID, BK2DSRM, BKDSRM, BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).
0x1: B_0x1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
Bit 12: Break enable This bit enables the complete break protection (including all sources connected to bk_acth and BKIN sources, as per ). Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break function disabled
0x1: B_0x1: Break function enabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. In response to a break event or if MOE is written to 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. See OC/OCN enable description for more details (enable register (TIM1_CCERTIMx_CCER)N/A)..
Allowed values:
0x0: B_0x0: In response to a break 2 event. OC and OCN outputs are disabled
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 20-23: Break 2 filter This bit-field defines the frequency used to sample BRK2 input and the length of the digital filter applied to BRK2. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: No filter, BRK2 acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bit 24: Break 2 enable Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK2 disabled
0x1: B_0x1: Break input BRK2 enabled
Bit 25: Break 2 polarity Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK2 is active low
0x1: B_0x1: Break input BRK2 is active high
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,
Bits 8-12: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ... Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIMx_CR1. If DBL = 7 bytes and DBA = TIMx_CR1 represents the address of the byte to be transferred, the address of the transfer should be given by the following equation: (TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address from/to which the data is copied. In this case, the transfer is done to 7 registers starting from the following address: (TIMx_CR1 address) + DBA According to the configuration of the DMA Data Size, several cases may occur: If the DMA Data Size is configured in half-words, 16-bit data is transferred to each of the 7 registers. If the DMA Data Size is configured in bytes, the data is also transferred to 7 registers: the first register contains the first MSB byte, the second register, the first LSB byte and so on. So with the transfer Timer, one also has to specify the size of data transferred by DMA..
Allowed values:
0x0: B_0x0: 1 transfer
0x1: B_0x1: 2 transfers
0x2: B_0x2: 3 transfers
0x11: B_0x11: 18 transfers
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
DMAB
rw |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
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Bits 0-31: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR)..
option register 1
Offset: 0x50, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OCREF_CLR
rw |
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capture/compare mode register 2 (output mode)
Offset: 0x54, reset: 0x00000000, access: read-write
4/10 fields covered.
Bits 4-6: Output compare 5 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 12-14: Output compare 6 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare register 4
Offset: 0x58, reset: 0x00000000, access: read-write
3/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
GC5C3
rw |
GC5C2
rw |
GC5C1
rw |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR5
rw |
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Bits 0-15: Capture/Compare 5 value CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC5 output..
Bit 29: Group Channel 5 and Channel 1 Distortion on Channel 1 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Allowed values:
0x0: B_0x0: No effect of OC5REF on OC1REFC5
0x1: B_0x1: OC1REFC is the logical AND of OC1REFC and OC5REF
Bit 30: Group Channel 5 and Channel 2 Distortion on Channel 2 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR1). Note: it is also possible to apply this distortion on combined PWM signals..
Allowed values:
0x0: B_0x0: No effect of OC5REF on OC2REFC
0x1: B_0x1: OC2REFC is the logical AND of OC2REFC and OC5REF
Bit 31: Group Channel 5 and Channel 3 Distortion on Channel 3 output: This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2). Note: it is also possible to apply this distortion on combined PWM signals..
Allowed values:
0x0: B_0x0: No effect of OC5REF on OC3REFC
0x1: B_0x1: OC3REFC is the logical AND of OC3REFC and OC5REF
capture/compare register 4
Offset: 0x5c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR6
rw |
|||||||||||||||
DMA address for full transfer
Offset: 0x60, reset: 0x00000001, access: read-write
7/7 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: BKIN input polarity is inverted (active high if BKP=0, active low if BKP=1)
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: COMP1 input polarity is inverted (active high if BKP=0, active low if BKP=1)
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input polarity is not inverted (active low if BKP=0, active high if BKP=1)
0x1: B_0x1: COMP2 input polarity is inverted (active high if BKP=0, active low if BKP=1)
Bits 14-17: ETR source selection These bits select the ETR input source. Others: Reserved Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: ETR legacy mode
0x1: B_0x1: COMP1 output
0x2: B_0x2: COMP2 output
0x3: B_0x3: ADC1 AWD1
0x4: B_0x4: ADC1 AWD2
0x5: B_0x5: ADC1 AWD3
DMA address for full transfer
Offset: 0x64, reset: 0x00000001, access: read-write
6/6 fields covered.
Bit 0: BRK2 BKIN input enable This bit enables the BKIN2 alternate function input for the timerâs BRK2 input. BKIN2 input is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN2 input disabled
0x1: B_0x1: BKIN2 input enabled
Bit 1: BRK2 COMP1 enable This bit enables the COMP1 for the timerâs BRK2 input. COMP1 output is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled
Bit 2: BRK2 COMP2 enable This bit enables the COMP2 for the timerâs BRK2 input. COMP2 output is 'ORedâ with the other BRK2 sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled
Bit 9: BRK2 BKIN2 input polarity This bit selects the BKIN2 alternate function input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: BKIN2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
Bit 10: BRK2 COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: COMP1 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
Bit 11: BRK2 COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
0x1: B_0x1: COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
TIM1 timer input selection register
Offset: 0x68, reset: 0x00000000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TI4SEL
rw |
TI3SEL
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI2SEL
rw |
TI1SEL
rw |
||||||||||||||
0x40002000: General purpose timers
24/31 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
7/7 fields covered.
Bit 1: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. Counter overflow Setting the UG bit. Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. An UEV is generated by one of the following events:
0x1: B_0x1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 2: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. Counter overflow Setting the UG bit.
Allowed values:
0x0: B_0x0: Any of the following events generate an UEV if enabled:
0x1: B_0x1: Only counter overflow generates an UEV if enabled.
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1IE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1OF
rw |
CC1IF
rw |
UIF
rw |
|||||||||||||
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow and if UDIS=â0â in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=â0â and UDIS=â0â in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when he content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred.
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1G
w |
UG
w |
||||||||||||||
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.
Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..
Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events
Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/5 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output.
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1.
Bit 2: Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..
Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output compare 1 mode (refer to bit 16 for OC1M[3]) These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. Others: Reserved Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
2/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1P
rw |
CC1E
rw |
|||||||||||||
Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
TIM timer input selection register
Offset: 0x68, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1SEL
rw |
|||||||||||||||
0x40014000: General purpose timers
73/97 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x38 | CCR2 | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
7/7 fields covered.
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt if enabled
Bits 8-9: Clock division This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx).
Allowed values:
0x0: B_0x0: tDTS = tCK_INT
0x1: B_0x1: tDTS = 2*tCK_INT
0x2: B_0x2: tDTS = 4*tCK_INT
0x3: B_0x3: Reserved, do not program this value
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
8/8 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
Bits 4-6: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:.
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO).
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO).
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register)..
Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
1/5 fields covered.
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/slave mode.
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. Other codes: reserved. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=â00100â). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit field selects the trigger input to be used to synchronize the counter. Other: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
status register
Offset: 0x10, reset: 0x0000, access: read-write
6/8 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0x0: B_0x0: No trigger event occurred
0x1: B_0x1: Trigger interrupt pending
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
5/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/6 fields covered.
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..
Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events
Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
6/10 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output.
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1.
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2.
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..
Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..
Bits 8-9: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output.
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2.
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1.
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Bits 12-14: Output Compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / Reserved
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated. The OC1M[3] bit is not contiguous, located in bit 16..
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
4/7 fields covered.
Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..
Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin
Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, reset: 0x0000, access: read-write
10/11 fields covered.
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818)..
Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)
Bits 16-19: Break filter This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ....
Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM15 alternate register 1
Offset: 0x60, reset: 0x00000001, access: read-write
6/6 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high
input selection register
Offset: 0x68, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI2SEL
rw |
TI1SEL
rw |
||||||||||||||
0x40014400: General purpose timers
58/66 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
7/7 fields covered.
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
5/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
status register
Offset: 0x10, reset: 0x0000, access: read-write
5/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BG
w |
COMG
w |
CC1G
w |
UG
w |
||||||||||||
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A capture/compare event is generated on channel 1:
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..
Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input.
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events
Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
capture/compare mode register (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/5 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..
Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16..
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1NE
rw |
CC1P
rw |
CC1E
rw |
||||||||||||
Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..
Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin
Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..
Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, reset: 0x0000, access: read-write
10/11 fields covered.
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..
Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM17 option register 1
Offset: 0x60, reset: 0x00000001, access: read-write
6/6 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high
input selection register
Offset: 0x68, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1SEL
rw |
|||||||||||||||
0x40014800: General purpose timers
58/66 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x30 | RCR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x44 | BDTR | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
7/7 fields covered.
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 8-9: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (TIx),.
Allowed values:
0x0: B_0x0: tDTS=tCK_INT
0x1: B_0x1: tDTS=2*tCK_INT
0x2: B_0x2: tDTS=4*tCK_INT
0x3: B_0x3: Reserved, do not program this value
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
5/5 fields covered.
Bit 0: Capture/compare preloaded control Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: CCxE, CCxNE and OCxM bits are not preloaded
0x1: B_0x1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.
Bit 2: Capture/compare control update selection Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
0x1: B_0x1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
Bit 8: Output Idle state 1 (OC1 output) Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
0x1: B_0x1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
status register
Offset: 0x10, reset: 0x0000, access: read-write
5/5 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/Compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BG
w |
COMG
w |
CC1G
w |
UG
w |
||||||||||||
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
Bit 1: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A capture/compare event is generated on channel 1:
Bit 5: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware. Note: This bit acts only on channels that have a complementary output..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Bit 7: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
capture/compare mode register 1 (input mode)
Offset: 0x18, reset: 0x00000000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
IC1F
rw |
IC1PSC
rw |
CC1S
rw |
|||||||||||||
Bits 0-1: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
Bits 2-3: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=â0â (TIMx_CCER register)..
Allowed values:
0x0: B_0x0: no prescaler, capture is done each time an edge is detected on the capture input.
0x1: B_0x1: capture is done once every 2 events
0x2: B_0x2: capture is done once every 4 events
0x3: B_0x3: capture is done once every 8 events
Bits 4-7: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
capture/compare mode register (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
4/5 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = '0â in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
Bit 2: Output Compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger..
Allowed values:
0x0: B_0x0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
0x1: B_0x1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode.
Bit 3: Output Compare 1 preload enable Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy
4: ForceInactive: OCyREF is forced low
5: ForceActive: OCyREF is forced high
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1
Bit 16: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. All other values: Reserved Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. The OC1M[3] bit is not contiguous, located in bit 16..
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CC1NP
rw |
CC1NE
rw |
CC1P
rw |
CC1E
rw |
||||||||||||
Bit 0: Capture/Compare 1 output enable When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details..
Allowed values:
0x0: B_0x0: Capture mode disabled / OC1 is not active (see below)
0x1: B_0x1: Capture mode enabled / OC1 signal is output on the corresponding output pin
Bit 1: Capture/Compare 1 output polarity When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: this configuration is reserved, it must not be used. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
Bit 2: Capture/Compare 1 complementary output enable.
Allowed values:
0x0: B_0x0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
0x1: B_0x1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Bit 3: Capture/Compare 1 complementary output polarity CC1 channel configured as output: CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â00â (the channel is configured in output). On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated..
Allowed values:
0x0: B_0x0: OC1N active high
0x1: B_0x1: OC1N active low
counter
Offset: 0x24, reset: 0x00000000, access: Unspecified
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
repetition counter register
Offset: 0x30, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
REP
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
break and dead-time register
Offset: 0x44, reset: 0x0000, access: read-write
10/11 fields covered.
Bits 0-7: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register)..
Bits 8-9: Lock configuration These bits offer a write protection against software errors. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset..
Allowed values:
0x0: B_0x0: LOCK OFF - No bit is write protected
0x1: B_0x1: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
0x2: B_0x2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
0x3: B_0x3: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
Bit 10: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
0x1: B_0x1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Bit 11: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
0x1: B_0x1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
Bit 12: Break enable 1; Break inputs (BRK and CCS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break inputs (BRK and CCS clock failure event) disabled
Bit 13: Break polarity Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is active low
0x1: B_0x1: Break input BRK is active high
Bit 14: Automatic output enable Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: MOE can be set only by software
0x1: B_0x1: MOE can be set by software or automatically at the next update event (if the break input is not be active)
Bit 15: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. enable register (TIM16_CCER)(TIMx_CCER)(x = 16 to 17) on page 846)..
Allowed values:
0x0: B_0x0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
0x1: B_0x1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)See OC/OCN enable description for more details (
Bits 16-19: Break filter This bit-field defines the frequency used to sample BRK input and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: No filter, BRK acts asynchronously
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bit 26: Break Disarm This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK is armed
0x1: B_0x1: Break input BRK is disarmed
Bit 28: Break Bidirectional In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective..
Allowed values:
0x0: B_0x0: Break input BRK in input mode
0x1: B_0x1: Break input BRK in bidirectional mode
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values:
0x0: B_0x0: TIMx_CR1,
0x1: B_0x1: TIMx_CR2,
0x2: B_0x2: TIMx_SMCR,
Bits 8-12: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM17 option register 1
Offset: 0x60, reset: 0x00000001, access: read-write
6/6 fields covered.
Bit 0: BRK BKIN input enable This bit enables the BKIN alternate function input for the timerâs BRK input. BKIN input is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input disabled
0x1: B_0x1: BKIN input enabled
Bit 1: BRK COMP1 enable This bit enables the COMP1 for the timerâs BRK input. COMP1 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input disabled
0x1: B_0x1: COMP1 input enabled
Bit 2: BRK COMP2 enable This bit enables the COMP2 for the timerâs BRK input. COMP2 output is 'ORedâ with the other BRK sources. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input disabled
0x1: B_0x1: COMP2 input enabled
Bit 9: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: BKIN input is active low
0x1: B_0x1: BKIN input is active high
Bit 10: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP1 input is active low
0x1: B_0x1: COMP1 input is active high
Bit 11: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)..
Allowed values:
0x0: B_0x0: COMP2 input is active low
0x1: B_0x1: COMP2 input is active high
input selection register
Offset: 0x68, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1SEL
rw |
|||||||||||||||
0x40000000: General-purpose-timers
59/115 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x24 | CNT_ALTERNATE5 | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x38 | CCR2 | ||||||||||||||||||||||||||||||||
| 0x3c | CCR3 | ||||||||||||||||||||||||||||||||
| 0x40 | CCR4 | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR1 | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
9/9 fields covered.
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
6/10 fields covered.
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/Slave mode.
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
status register
Offset: 0x10, reset: 0x0000, access: read-write
4/10 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
3/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
8/12 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output.
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2.
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1.
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare mode register 2 (input mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
2/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
4/12 fields covered.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
2/12 fields covered.
Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT_L
rw |
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counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
rw |
CNT
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
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prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
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auto-reload register
Offset: 0x2c, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
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Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..
capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..
capture/compare register 3
Offset: 0x3c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR3
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..
capture/compare register 4
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR4
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR4
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values:
0x0: B_0x0: TIMx_CR1
0x1: B_0x1: TIMx_CR2
0x2: B_0x2: TIMx_SMCR
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM option register
Offset: 0x50, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OCREF_CLR
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x60, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ETRSEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ETRSEL
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x68, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI2SEL
rw |
TI1SEL
rw |
||||||||||||||
0x40000400: General-purpose-timers
59/115 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x24 | CNT_ALTERNATE5 | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x38 | CCR2 | ||||||||||||||||||||||||||||||||
| 0x3c | CCR3 | ||||||||||||||||||||||||||||||||
| 0x40 | CCR4 | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR1 | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
9/9 fields covered.
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
6/10 fields covered.
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/Slave mode.
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
status register
Offset: 0x10, reset: 0x0000, access: read-write
4/10 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
3/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
8/12 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output.
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2.
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1.
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare mode register 2 (input mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
2/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
4/12 fields covered.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
2/12 fields covered.
Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT_L
rw |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
rw |
CNT
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..
capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..
capture/compare register 3
Offset: 0x3c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR3
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..
capture/compare register 4
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR4
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR4
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values:
0x0: B_0x0: TIMx_CR1
0x1: B_0x1: TIMx_CR2
0x2: B_0x2: TIMx_SMCR
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM option register
Offset: 0x50, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OCREF_CLR
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x60, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ETRSEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ETRSEL
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x68, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI2SEL
rw |
TI1SEL
rw |
||||||||||||||
0x40000800: General-purpose-timers
59/115 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | SMCR | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Input | ||||||||||||||||||||||||||||||||
| 0x18 | CCMR1_Output | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Input | ||||||||||||||||||||||||||||||||
| 0x1c | CCMR2_Output | ||||||||||||||||||||||||||||||||
| 0x20 | CCER | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x24 | CNT_ALTERNATE5 | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
| 0x34 | CCR1 | ||||||||||||||||||||||||||||||||
| 0x38 | CCR2 | ||||||||||||||||||||||||||||||||
| 0x3c | CCR3 | ||||||||||||||||||||||||||||||||
| 0x40 | CCR4 | ||||||||||||||||||||||||||||||||
| 0x48 | DCR | ||||||||||||||||||||||||||||||||
| 0x4c | DMAR | ||||||||||||||||||||||||||||||||
| 0x50 | OR1 | ||||||||||||||||||||||||||||||||
| 0x60 | AF1 | ||||||||||||||||||||||||||||||||
| 0x68 | TISEL | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
9/9 fields covered.
Bit 0: Counter enable Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bits 5-6: Center-aligned mode selection Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1).
Allowed values:
0x0: B_0x0: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).
0x1: B_0x1: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down.
0x2: B_0x2: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up.
0x3: B_0x3: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI1S
rw |
MMS
rw |
CCDS
rw |
|||||||||||||
Bits 4-6: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
0x3: B_0x3: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)
0x4: B_0x4: Compare - OC1REFC signal is used as trigger output (TRGO)
0x5: B_0x5: Compare - OC2REFC signal is used as trigger output (TRGO)
0x6: B_0x6: Compare - OC3REFC signal is used as trigger output (TRGO)
0x7: B_0x7: Compare - OC4REFC signal is used as trigger output (TRGO)
slave mode control register
Offset: 0x8, reset: 0x0000, access: read-write
6/10 fields covered.
Bits 0-2: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 4-6: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
Bit 7: Master/Slave mode.
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Bits 8-11: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:.
Allowed values:
0x0: B_0x0: No filter, sampling is done at fDTS
0x1: B_0x1: fSAMPLING=fCK_INT, N=2
0x2: B_0x2: fSAMPLING=fCK_INT, N=4
0x3: B_0x3: fSAMPLING=fCK_INT, N=8
0x4: B_0x4: fSAMPLING=fDTS/2, N=6
0x5: B_0x5: fSAMPLING=fDTS/2, N=8
0x6: B_0x6: fSAMPLING=fDTS/4, N=6
0x7: B_0x7: fSAMPLING=fDTS/4, N=8
0x8: B_0x8: fSAMPLING=fDTS/8, N=6
0x9: B_0x9: fSAMPLING=fDTS/8, N=8
0xA: B_0xA: fSAMPLING=fDTS/16, N=5
0xB: B_0xB: fSAMPLING=fDTS/16, N=6
0xC: B_0xC: fSAMPLING=fDTS/16, N=8
0xD: B_0xD: fSAMPLING=fDTS/32, N=5
0xE: B_0xE: fSAMPLING=fDTS/32, N=6
0xF: B_0xF: fSAMPLING=fDTS/32, N=8
Bits 12-13: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks..
Allowed values:
0x0: B_0x0: Prescaler OFF
0x1: B_0x1: ETRP frequency divided by 2
0x2: B_0x2: ETRP frequency divided by 4
0x3: B_0x3: ETRP frequency divided by 8
Bit 14: External clock enable This bit enables External clock mode 2. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=00111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 00111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF..
Allowed values:
0x0: B_0x0: External clock mode 2 disabled
0x1: B_0x1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.
Bit 16: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. reinitializes the counter, generates an update of the registers and starts the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer..
Bits 20-21: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. Others: Reserved See for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition..
status register
Offset: 0x10, reset: 0x0000, access: read-write
4/10 fields covered.
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
Bit 1: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description. If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER)..
Allowed values:
0x0: B_0x0: No compare match / No input capture occurred
0x1: B_0x1: A compare match or an input capture occurred
Bit 6: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software..
Allowed values:
0x0: B_0x0: No trigger event occurred.
0x1: B_0x1: Trigger interrupt pending.
Bit 9: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0â..
Allowed values:
0x0: B_0x0: No overcapture has been detected.
0x1: B_0x1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
3/6 fields covered.
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting).
Bit 1: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high..
Allowed values:
0x0: B_0x0: No action
0x1: B_0x1: A capture/compare event is generated on channel 1:
capture/compare mode register 1 (output mode)
Offset: 0x18, reset: 0x00000000, access: read-write
8/12 fields covered.
Bits 0-1: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC1 channel is configured as output
0x1: B_0x1: CC1 channel is configured as input, IC1 is mapped on TI1
0x2: B_0x2: CC1 channel is configured as input, IC1 is mapped on TI2
0x3: B_0x3: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bit 3: Output compare 1 preload enable Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed..
Allowed values:
0x0: B_0x0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
0x1: B_0x1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Bits 4-6: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. Note: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from âfrozenâ mode to âPWMâ mode. Note: The OC1M[3] bit is not contiguous, located in bit 16..
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 8-9: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC2 channel is configured as output.
0x1: B_0x1: CC2 channel is configured as input, IC2 is mapped on TI2.
0x2: B_0x2: CC2 channel is configured as input, IC2 is mapped on TI1.
0x3: B_0x3: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 12-14: Output compare 2 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare mode register 2 (input mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
2/6 fields covered.
Bits 0-1: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC3 channel is configured as output
0x1: B_0x1: CC3 channel is configured as input, IC3 is mapped on TI3
0x2: B_0x2: CC3 channel is configured as input, IC3 is mapped on TI4
0x3: B_0x3: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
Bits 8-9: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER)..
Allowed values:
0x0: B_0x0: CC4 channel is configured as output
0x1: B_0x1: CC4 channel is configured as input, IC4 is mapped on TI4
0x2: B_0x2: CC4 channel is configured as input, IC4 is mapped on TI3
0x3: B_0x3: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
capture/compare mode register 2 (output mode)
Offset: 0x1c, reset: 0x00000000, access: read-write
4/12 fields covered.
Bits 4-6: Output compare 3 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
Bits 12-14: Output compare 4 mode.
Allowed values:
0: Frozen: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive
1: ActiveOnMatch: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1
2: InactiveOnMatch: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved
3: Toggle: OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved
4: ForceInactive: OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF
5: ForceActive: OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF
6: PwmMode1: In upcounting, channel is active as long as TIMx_CNT
7: PwmMode2: Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1
capture/compare enable register
Offset: 0x20, reset: 0x0000, access: read-write
2/12 fields covered.
Bit 1: Capture/Compare 1 output Polarity. When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode). CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode). CC1NP=1, CC1P=1: non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode. CC1NP=1, CC1P=0: This configuration is reserved, it must not be used..
Allowed values:
0x0: B_0x0: OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
0x1: B_0x1: OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CNT_H
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT_L
rw |
|||||||||||||||
counter
Offset: 0x24, reset: 0x00000000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
rw |
CNT
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0xFFFFFFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ARR
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
capture/compare register 1
Offset: 0x34, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR1
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 1 value (TIM2) nullLow Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). The TIMx_CCR1 register is read-only and cannot be programmed..
capture/compare register 2
Offset: 0x38, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR2
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 2 value (TIM2) nullLow Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). The TIMx_CCR2 register is read-only and cannot be programmed..
capture/compare register 3
Offset: 0x3c, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR3
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR3
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 3 value (TIM2) nullLow Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). The TIMx_CCR3 register is read-only and cannot be programmed..
capture/compare register 4
Offset: 0x40, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CCR4
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CCR4
rw |
|||||||||||||||
Bits 0-31: High Capture/Compare 4 value (TIM2) nullLow Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). The TIMx_CCR4 register is read-only and cannot be programmed..
DMA control register
Offset: 0x48, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBL
rw |
DBA
rw |
||||||||||||||
Bits 0-4: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address..
Allowed values:
0x0: B_0x0: TIMx_CR1
0x1: B_0x1: TIMx_CR2
0x2: B_0x2: TIMx_SMCR
Bits 8-12: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). ....
Allowed values:
0x0: B_0x0: 1 transfer,
0x1: B_0x1: 2 transfers,
0x2: B_0x2: 3 transfers,
0x11: B_0x11: 18 transfers.
DMA address for full transfer
Offset: 0x4c, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DMAB
rw |
|||||||||||||||
TIM option register
Offset: 0x50, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
OCREF_CLR
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x60, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
ETRSEL
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ETRSEL
rw |
|||||||||||||||
TIM alternate function option register 1
Offset: 0x68, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TI2SEL
rw |
TI1SEL
rw |
||||||||||||||
0x40001000: Basic timers
12/15 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
6/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x40001400: Basic timers
12/15 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0xc | DIER | ||||||||||||||||||||||||||||||||
| 0x10 | SR | ||||||||||||||||||||||||||||||||
| 0x14 | EGR | ||||||||||||||||||||||||||||||||
| 0x24 | CNT | ||||||||||||||||||||||||||||||||
| 0x28 | PSC | ||||||||||||||||||||||||||||||||
| 0x2c | ARR | ||||||||||||||||||||||||||||||||
control register 1
Offset: 0x0, reset: 0x0000, access: read-write
6/6 fields covered.
Bit 0: Counter enable Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs..
Allowed values:
0x0: B_0x0: Counter disabled
0x1: B_0x1: Counter enabled
Bit 1: Update disable This bit is set and cleared by software to enable/disable UEV event generation. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values..
Allowed values:
0x0: B_0x0: UEV enabled. The Update (UEV) event is generated by one of the following events:
0x1: B_0x1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 2: Update request source This bit is set and cleared by software to select the UEV event sources. Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller.
Allowed values:
0x0: B_0x0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be:
0x1: B_0x1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
control register 2
Offset: 0x4, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
MMS
rw |
|||||||||||||||
Bits 4-6: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). Note: The clock of the slave timer or ADC must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer..
Allowed values:
0x0: B_0x0: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
0x1: B_0x1: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
0x2: B_0x2: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
DMA/Interrupt enable register
Offset: 0xc, reset: 0x0000, access: read-write
2/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UDE
rw |
UIE
rw |
||||||||||||||
status register
Offset: 0x10, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UIF
rw |
|||||||||||||||
Bit 0: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register..
Allowed values:
0x0: B_0x0: No update occurred.
0x1: B_0x1: Update interrupt pending. This bit is set by hardware when the registers are updated:
event generation register
Offset: 0x14, reset: 0x0000, access: write-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
UG
w |
|||||||||||||||
Bit 0: Update generation This bit can be set by software, it is automatically cleared by hardware..
Allowed values:
0x0: B_0x0: No action.
0x1: B_0x1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).
counter
Offset: 0x24, reset: 0x00000000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UIFCPY
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
CNT
rw |
|||||||||||||||
prescaler
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PSC
rw |
|||||||||||||||
auto-reload register
Offset: 0x2c, reset: 0x0000FFFF, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
ARR
rw |
|||||||||||||||
0x4000a000: USB Power Delivery interface
65/91 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CFGR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CFGR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CFGR3 | ||||||||||||||||||||||||||||||||
| 0xc | CR | ||||||||||||||||||||||||||||||||
| 0x10 | IMR | ||||||||||||||||||||||||||||||||
| 0x14 | SR | ||||||||||||||||||||||||||||||||
| 0x18 | ICR | ||||||||||||||||||||||||||||||||
| 0x1c | TX_ORDSETR | ||||||||||||||||||||||||||||||||
| 0x20 | TX_PAYSZR | ||||||||||||||||||||||||||||||||
| 0x24 | TXDR | ||||||||||||||||||||||||||||||||
| 0x28 | RX_ORDSETR | ||||||||||||||||||||||||||||||||
| 0x2c | RX_PAYSZR | ||||||||||||||||||||||||||||||||
| 0x30 | RXDR | ||||||||||||||||||||||||||||||||
| 0x34 | RX_ORDEXTR1 | ||||||||||||||||||||||||||||||||
| 0x38 | RX_ORDEXTR2 | ||||||||||||||||||||||||||||||||
UCPD configuration register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
7/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UCPDEN
rw |
RXDMAEN
rw |
TXDMAEN
rw |
RXORDSETEN
rw |
PSC_USBPDCLK
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRANSWIN
rw |
IFRGAP
rw |
HBITCLKDIV
rw |
|||||||||||||
Bits 6-10: Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal..
Allowed values:
0x0: B_0x0: Not supported
0x1: B_0x1: 2
0xD: B_0xD: 14
0xE: B_0xE: 15
0xF: B_0xF: 16
0x1F: B_0x1F: 32
Bits 11-15: Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting..
Allowed values:
0x0: B_0x0: Not supported
0x1: B_0x1: 2
0x9: B_0x9: 10 (recommended)
0x1F: B_0x1F: 32
Bits 17-19: Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz..
Allowed values:
0x0: B_0x0: 1 (bypass)
0x1: B_0x1: 2
0x2: B_0x2: 4
0x3: B_0x3: 8
0x4: B_0x4: 16
Bits 20-28: Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled.
Bit 31: UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state..
Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable
UCPD configuration register 2
Offset: 0x4, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUPEN
rw |
FORCECLK
rw |
RXFILT2N3
rw |
RXFILTDIS
rw |
||||||||||||
UCPD configuration register 3
Offset: 0x8, reset: 0x00000000, access: Unspecified
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TRIM2_NG_CC3A0
rw |
TRIM2_NG_CC1A5
rw |
TRIM2_NG_CCRPD
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRIM1_NG_CC3A0
rw |
TRIM1_NG_CC1A5
rw |
TRIM1_NG_CCRPD
rw |
|||||||||||||
UCPD control register
Offset: 0xc, reset: 0x00000000, access: Unspecified
16/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC2TCDIS
rw |
CC1TCDIS
rw |
RDCH
rw |
FRSTX
rw |
FRSRXEN
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBATTEN
rw |
CC2VCONNEN
rw |
CC1VCONNEN
rw |
CCENABLE
rw |
ANAMODE
rw |
ANASUBMODE
rw |
PHYCCSEL
rw |
PHYRXEN
rw |
RXMODE
rw |
TXHRST
rw |
TXSEND
rw |
TXMODE
rw |
||||
Bits 0-1: Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the peripheral (UCPDEN = 0)..
Allowed values:
0x0: B_0x0: Transmission of Tx packet previously defined in other registers
0x1: B_0x1: Cable Reset sequence
0x2: B_0x2: BIST test sequence (BIST Carrier Mode 2)
Bit 4: Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message..
Allowed values:
0x0: B_0x0: Normal receive mode
0x1: B_0x1: BIST receive mode (BIST test data mode)
Bit 9: Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]..
Allowed values:
0x0: B_0x0: Source
0x1: B_0x1: Sink
Bits 10-11: CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source..
Allowed values:
0x0: B_0x0: Disable both PHYs
0x1: B_0x1: Enable CC1 PHY
0x2: B_0x2: Enable CC2 PHY
0x3: B_0x3: Enable CC1 and CC2 PHY
Bit 18: Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register..
Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Rdch condition drive
UCPD interrupt mask register
Offset: 0x10, reset: 0x00000000, access: Unspecified
14/15 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FRSEVTIE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TYPECEVT2IE
rw |
TYPECEVT1IE
rw |
RXMSGENDIE
rw |
RXOVRIE
rw |
RXHRSTDETIE
rw |
RXORDDETIE
rw |
RXNEIE
rw |
TXUNDIE
rw |
HRSTSENTIE
rw |
HRSTDISCIE
rw |
TXMSGABTIE
rw |
TXMSGSENTIE
rw |
TXMSGDISCIE
rw |
TXISIE
rw |
||
UCPD status register
Offset: 0x14, reset: 0x00000000, access: Unspecified
18/18 fields covered.
Bit 0: Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register..
Allowed values:
0x0: B_0x0: New Tx data write not required
0x1: B_0x1: New Tx data write required
Bit 1: Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle..
Allowed values:
0x0: B_0x0: No Tx message discarded
0x1: B_0x1: Tx message discarded
Bit 2: Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised..
Allowed values:
0x0: B_0x0: No Tx message completed
0x1: B_0x1: Tx message completed
Bit 3: Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit..
Allowed values:
0x0: B_0x0: No transmit message abort
0x1: B_0x1: Transmit message abort
Bit 6: Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit..
Allowed values:
0x0: B_0x0: No Tx data underrun detected
0x1: B_0x1: Tx data underrun detected
Bit 9: Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit..
Allowed values:
0x0: B_0x0: No ordered set detected
0x1: B_0x1: A new ordered set detected
Bit 12: Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message..
Allowed values:
0x0: B_0x0: No new Rx message received
0x1: B_0x1: A new Rx message received
Bit 13: Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set..
Allowed values:
0x0: B_0x0: No error detected
0x1: B_0x1: Error(s) detected
Bits 16-17: The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value..
Allowed values:
0x0: B_0x0: Lowest
0x1: B_0x1: Low
0x2: B_0x2: High
0x3: B_0x3: Highest
Bits 18-19: CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value..
Allowed values:
0x0: B_0x0: Lowest
0x1: B_0x1: Low
0x2: B_0x2: High
0x3: B_0x3: Highest
UCPD interrupt clear register
Offset: 0x18, reset: 0x00000000, access: Unspecified
0/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FRSEVTCF
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TYPECEVT2CF
w |
TYPECEVT1CF
w |
RXMSGENDCF
w |
RXOVRCF
w |
RXHRSTDETCF
w |
RXORDDETCF
w |
TXUNDCF
w |
HRSTSENTCF
w |
HRSTDISCCF
w |
TXMSGABTCF
w |
TXMSGSENTCF
w |
TXMSGDISCCF
w |
||||
UCPD Tx ordered set type register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXORDSET
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXORDSET
rw |
|||||||||||||||
UCPD Tx payload size register
Offset: 0x20, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXPAYSZ
rw |
|||||||||||||||
Bits 0-9: Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the UCPD_TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission..
Allowed values:
0x2: B_0x2: 2 bytes - the size of Control message from the protocol layer
0x6: B_0x6: 6 bytes - the shortest Data message allowed from the protocol layer)
0x1E: B_0x1E: 30 bytes - the longest non-extended Data message allowed from the protocol layer
0x106: B_0x106: 262 bytes - the longest possible extended message
0x3FF: B_0x3FF: 1024 bytes - the longest possible payload (for future expansion)
UCPD Tx data register
Offset: 0x24, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
UCPD Rx ordered set register
Offset: 0x28, reset: 0x00000000, access: Unspecified
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPKINVALID
r |
RXSOP3OF4
r |
RXORDSET
r |
|||||||||||||
Bits 0-2: Rx ordered set code detected.
Allowed values:
0x0: B_0x0: SOP code detected in receiver
0x1: B_0x1: SOP' code detected in receiver
0x2: B_0x2: SOP'' code detected in receiver
0x3: B_0x3: SOP'_Debug detected in receiver
0x4: B_0x4: SOP''_Debug detected in receiver
0x5: B_0x5: Cable Reset detected in receiver
0x6: B_0x6: SOP extension#1 detected in receiver
0x7: B_0x7: SOP extension#2 detected in receiver
UCPD Rx payload size register
Offset: 0x2c, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXPAYSZ
r |
|||||||||||||||
Bits 0-9: Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the UCPD_RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)..
Allowed values:
0x2: B_0x2: 2 bytes - the size of Control message from the protocol layer
0x6: B_0x6: 6 bytes - the shortest Data message allowed from the protocol layer)
0x1E: B_0x1E: 30 bytes - the longest non-extended Data message allowed from the protocol layer
0x106: B_0x106: 262 bytes - the longest possible extended message
0x3FF: B_0x3FF: 1024 bytes - the longest possible payload (for future expansion)
UCPD receive data register
Offset: 0x30, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
UCPD Rx ordered set extension register 1
Offset: 0x34, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXSOPX1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPX1
rw |
|||||||||||||||
UCPD Rx ordered set extension register 2
Offset: 0x38, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXSOPX2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPX2
rw |
|||||||||||||||
0x4000a400: USB Power Delivery interface
65/91 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CFGR1 | ||||||||||||||||||||||||||||||||
| 0x4 | CFGR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CFGR3 | ||||||||||||||||||||||||||||||||
| 0xc | CR | ||||||||||||||||||||||||||||||||
| 0x10 | IMR | ||||||||||||||||||||||||||||||||
| 0x14 | SR | ||||||||||||||||||||||||||||||||
| 0x18 | ICR | ||||||||||||||||||||||||||||||||
| 0x1c | TX_ORDSETR | ||||||||||||||||||||||||||||||||
| 0x20 | TX_PAYSZR | ||||||||||||||||||||||||||||||||
| 0x24 | TXDR | ||||||||||||||||||||||||||||||||
| 0x28 | RX_ORDSETR | ||||||||||||||||||||||||||||||||
| 0x2c | RX_PAYSZR | ||||||||||||||||||||||||||||||||
| 0x30 | RXDR | ||||||||||||||||||||||||||||||||
| 0x34 | RX_ORDEXTR1 | ||||||||||||||||||||||||||||||||
| 0x38 | RX_ORDEXTR2 | ||||||||||||||||||||||||||||||||
UCPD configuration register 1
Offset: 0x0, reset: 0x00000000, access: Unspecified
7/8 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
UCPDEN
rw |
RXDMAEN
rw |
TXDMAEN
rw |
RXORDSETEN
rw |
PSC_USBPDCLK
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRANSWIN
rw |
IFRGAP
rw |
HBITCLKDIV
rw |
|||||||||||||
Bits 6-10: Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a ucpd_clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal..
Allowed values:
0x0: B_0x0: Not supported
0x1: B_0x1: 2
0xD: B_0xD: 14
0xE: B_0xE: 15
0xF: B_0xF: 16
0x1F: B_0x1F: 32
Bits 11-15: Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the ucpd_clk frequency and the HBITCLKDIV[5:0] bitfield setting..
Allowed values:
0x0: B_0x0: Not supported
0x1: B_0x1: 2
0x9: B_0x9: 10 (recommended)
0x1F: B_0x1F: 32
Bits 17-19: Pre-scaler division ratio for generating ucpd_clk The bitfield determines the division ratio of a kernel clock pre-scaler producing UCPD peripheral clock (ucpd_clk). It is recommended to use the pre-scaler so as to set the ucpd_clk frequency in the range from 6 to 9 MHz..
Allowed values:
0x0: B_0x0: 1 (bypass)
0x1: B_0x1: 2
0x2: B_0x2: 4
0x3: B_0x3: 8
0x4: B_0x4: 16
Bits 20-28: Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP' detect enabled 0bxxxxxx1xx: SOP'' detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP'_Debug enabled 0bxx1xxxxxx: SOP''_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled.
Bit 31: UCPD peripheral enable General enable of the UCPD peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state..
Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable
UCPD configuration register 2
Offset: 0x4, reset: 0x00000000, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WUPEN
rw |
FORCECLK
rw |
RXFILT2N3
rw |
RXFILTDIS
rw |
||||||||||||
UCPD configuration register 3
Offset: 0x8, reset: 0x00000000, access: Unspecified
0/6 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TRIM2_NG_CC3A0
rw |
TRIM2_NG_CC1A5
rw |
TRIM2_NG_CCRPD
rw |
|||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRIM1_NG_CC3A0
rw |
TRIM1_NG_CC1A5
rw |
TRIM1_NG_CCRPD
rw |
|||||||||||||
UCPD control register
Offset: 0xc, reset: 0x00000000, access: Unspecified
16/17 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
CC2TCDIS
rw |
CC1TCDIS
rw |
RDCH
rw |
FRSTX
rw |
FRSRXEN
rw |
|||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DBATTEN
rw |
CC2VCONNEN
rw |
CC1VCONNEN
rw |
CCENABLE
rw |
ANAMODE
rw |
ANASUBMODE
rw |
PHYCCSEL
rw |
PHYRXEN
rw |
RXMODE
rw |
TXHRST
rw |
TXSEND
rw |
TXMODE
rw |
||||
Bits 0-1: Type of Tx packet Writing the bitfield triggers the action as follows, depending on the value: Others: invalid From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the peripheral (UCPDEN = 0)..
Allowed values:
0x0: B_0x0: Transmission of Tx packet previously defined in other registers
0x1: B_0x1: Cable Reset sequence
0x2: B_0x2: BIST test sequence (BIST Carrier Mode 2)
Bit 4: Receiver mode Determines the mode of the receiver. When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message..
Allowed values:
0x0: B_0x0: Normal receive mode
0x1: B_0x1: BIST receive mode (BIST test data mode)
Bit 9: Analog PHY operating mode The bit takes effect upon setting the UCPDx_STROBE bit of the SYS_CONFIG register. The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0]..
Allowed values:
0x0: B_0x0: Source
0x1: B_0x1: Sink
Bits 10-11: CC line enable This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting. A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source..
Allowed values:
0x0: B_0x0: Disable both PHYs
0x1: B_0x1: Enable CC1 PHY
0x2: B_0x2: Enable CC2 PHY
0x3: B_0x3: Enable CC1 and CC2 PHY
Bit 18: Rdch condition drive The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to "USB Type-C ECN for Source VCONN Discharge". The CCENABLE[1:0] bitfield must be set accordingly, too. Changing the bit value only takes effect upon setting the UCPDx_STROBE bit of the SYSCFG_CFGR1 register..
Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Rdch condition drive
UCPD interrupt mask register
Offset: 0x10, reset: 0x00000000, access: Unspecified
14/15 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FRSEVTIE
r |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TYPECEVT2IE
rw |
TYPECEVT1IE
rw |
RXMSGENDIE
rw |
RXOVRIE
rw |
RXHRSTDETIE
rw |
RXORDDETIE
rw |
RXNEIE
rw |
TXUNDIE
rw |
HRSTSENTIE
rw |
HRSTDISCIE
rw |
TXMSGABTIE
rw |
TXMSGSENTIE
rw |
TXMSGDISCIE
rw |
TXISIE
rw |
||
UCPD status register
Offset: 0x14, reset: 0x00000000, access: Unspecified
18/18 fields covered.
Bit 0: Transmit interrupt status The flag indicates that the UCPD_TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the UCPD_TXDR register..
Allowed values:
0x0: B_0x0: New Tx data write not required
0x1: B_0x1: New Tx data write required
Bit 1: Message transmission discarded The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit. Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle..
Allowed values:
0x0: B_0x0: No Tx message discarded
0x1: B_0x1: Tx message discarded
Bit 2: Message transmission completed The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit. In the event of a message transmission interrupted by a Hard Reset, the flag is not raised..
Allowed values:
0x0: B_0x0: No Tx message completed
0x1: B_0x1: Tx message completed
Bit 3: Transmit message abort The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit..
Allowed values:
0x0: B_0x0: No transmit message abort
0x1: B_0x1: Transmit message abort
Bit 6: Tx data underrun detection The flag indicates that the Tx data register (UCPD_TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit..
Allowed values:
0x0: B_0x0: No Tx data underrun detected
0x1: B_0x1: Tx data underrun detected
Bit 9: Rx ordered set (4 K-codes) detection The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the UCPD_RX_ORDSET register. It is cleared by setting the RXORDDETCF bit..
Allowed values:
0x0: B_0x0: No ordered set detected
0x1: B_0x1: A new ordered set detected
Bit 12: Rx message received The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit. The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message..
Allowed values:
0x0: B_0x0: No new Rx message received
0x1: B_0x1: A new Rx message received
Bit 13: Receive message error The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set..
Allowed values:
0x0: B_0x0: No error detected
0x1: B_0x1: Error(s) detected
Bits 16-17: The status bitfield indicates the voltage level on the CC1 line in its steady state. The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value..
Allowed values:
0x0: B_0x0: Lowest
0x1: B_0x1: Low
0x2: B_0x2: High
0x3: B_0x3: Highest
Bits 18-19: CC2 line voltage level The status bitfield indicates the voltage level on the CC2 line in its steady state. The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value..
Allowed values:
0x0: B_0x0: Lowest
0x1: B_0x1: Low
0x2: B_0x2: High
0x3: B_0x3: Highest
UCPD interrupt clear register
Offset: 0x18, reset: 0x00000000, access: Unspecified
0/13 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
FRSEVTCF
w |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TYPECEVT2CF
w |
TYPECEVT1CF
w |
RXMSGENDCF
w |
RXOVRCF
w |
RXHRSTDETCF
w |
RXORDDETCF
w |
TXUNDCF
w |
HRSTSENTCF
w |
HRSTDISCCF
w |
TXMSGABTCF
w |
TXMSGSENTCF
w |
TXMSGDISCCF
w |
||||
UCPD Tx ordered set type register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXORDSET
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXORDSET
rw |
|||||||||||||||
UCPD Tx payload size register
Offset: 0x20, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXPAYSZ
rw |
|||||||||||||||
Bits 0-9: Payload size yet to transmit The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the UCPD_TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission..
Allowed values:
0x2: B_0x2: 2 bytes - the size of Control message from the protocol layer
0x6: B_0x6: 6 bytes - the shortest Data message allowed from the protocol layer)
0x1E: B_0x1E: 30 bytes - the longest non-extended Data message allowed from the protocol layer
0x106: B_0x106: 262 bytes - the longest possible extended message
0x3FF: B_0x3FF: 1024 bytes - the longest possible payload (for future expansion)
UCPD Tx data register
Offset: 0x24, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TXDATA
rw |
|||||||||||||||
UCPD Rx ordered set register
Offset: 0x28, reset: 0x00000000, access: Unspecified
3/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPKINVALID
r |
RXSOP3OF4
r |
RXORDSET
r |
|||||||||||||
Bits 0-2: Rx ordered set code detected.
Allowed values:
0x0: B_0x0: SOP code detected in receiver
0x1: B_0x1: SOP' code detected in receiver
0x2: B_0x2: SOP'' code detected in receiver
0x3: B_0x3: SOP'_Debug detected in receiver
0x4: B_0x4: SOP''_Debug detected in receiver
0x5: B_0x5: Cable Reset detected in receiver
0x6: B_0x6: SOP extension#1 detected in receiver
0x7: B_0x7: SOP extension#2 detected in receiver
UCPD Rx payload size register
Offset: 0x2c, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXPAYSZ
r |
|||||||||||||||
Bits 0-9: Rx payload size received This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the UCPD_RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled). The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low)..
Allowed values:
0x2: B_0x2: 2 bytes - the size of Control message from the protocol layer
0x6: B_0x6: 6 bytes - the shortest Data message allowed from the protocol layer)
0x1E: B_0x1E: 30 bytes - the longest non-extended Data message allowed from the protocol layer
0x106: B_0x106: 262 bytes - the longest possible extended message
0x3FF: B_0x3FF: 1024 bytes - the longest possible payload (for future expansion)
UCPD receive data register
Offset: 0x30, reset: 0x00000000, access: Unspecified
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXDATA
r |
|||||||||||||||
UCPD Rx ordered set extension register 1
Offset: 0x34, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXSOPX1
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPX1
rw |
|||||||||||||||
UCPD Rx ordered set extension register 2
Offset: 0x38, reset: 0x00000000, access: Unspecified
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
RXSOPX2
rw |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RXSOPX2
rw |
|||||||||||||||
0x40013800: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40004400: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40004800: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40004c00: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40005000: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40013c00: Universal synchronous asynchronous receiver transmitter
136/170 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR1_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x0 | CR1_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x4 | CR2 | ||||||||||||||||||||||||||||||||
| 0x8 | CR3 | ||||||||||||||||||||||||||||||||
| 0xc | BRR | ||||||||||||||||||||||||||||||||
| 0x10 | GTPR | ||||||||||||||||||||||||||||||||
| 0x14 | RTOR | ||||||||||||||||||||||||||||||||
| 0x18 | RQR | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_DISABLED | ||||||||||||||||||||||||||||||||
| 0x1c | ISR_FIFO_ENABLED | ||||||||||||||||||||||||||||||||
| 0x20 | ICR | ||||||||||||||||||||||||||||||||
| 0x24 | RDR | ||||||||||||||||||||||||||||||||
| 0x28 | TDR | ||||||||||||||||||||||||||||||||
| 0x2c | PRESC | ||||||||||||||||||||||||||||||||
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
18/22 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 1
Offset: 0x0, reset: 0x0000, access: read-write
20/24 fields covered.
Bit 0: USART enable When this bit is cleared, the USART prescalers and outputs are stopped immediately, and all current operations are discarded. The USART configuration is kept, but all the USART_ISR status flags are reset. This bit is set and cleared by software. Note: To enter low-power mode without generating errors on the line, the TE bit must be previously reset and the software must wait for the TC bit in the USART_ISR to be set before resetting the UE bit. The DMA requests are also reset when UE = 0 so the DMA channel must be disabled before resetting the UE bit. In Smartcard mode, (SCEN = 1), the SCLK is always available when CLKEN = 1, regardless of the UE bit value..
Allowed values:
0x0: B_0x0: USART prescaler and outputs disabled, low-power mode
0x1: B_0x1: USART enabled
Bit 1: USART enable in low-power mode When this bit is cleared, the USART cannot wake up the MCU from low-power mode. When this bit is set, the USART can wake up the MCU from low-power mode. This bit is set and cleared by software. Note: It is recommended to set the UESM bit just before entering low-power mode and clear it when exit from low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: USART not able to wake up the MCU from low-power mode.
0x1: B_0x1: USART able to wake up the MCU from low-power mode.
Bit 3: Transmitter enable This bit enables the transmitter. It is set and cleared by software. Note: During transmission, a low pulse on the TE bit ('0â followed by '1â) sends a preamble (idle line) after the current word, except in Smartcard mode. In order to generate an idle character, the TE must not be immediately written to '1â. To ensure the required duration, the software can poll the TEACK bit in the USART_ISR register. In Smartcard mode, when TE is set, there is a 1 bit-time delay before the transmission starts..
Allowed values:
0x0: B_0x0: Transmitter is disabled
0x1: B_0x1: Transmitter is enabled
Bit 9: Parity selection This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity is selected after the current byte. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Even parity
0x1: B_0x1: Odd parity
Bit 10: Parity control enable This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if MÂ =Â 1; 8th bit if MÂ =Â 0) and the parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Parity control disabled
0x1: B_0x1: Parity control enabled
Bit 13: Mute mode enable This bit enables the USART Mute mode function. When set, the USART can switch between active and Mute mode, as defined by the WAKE bit. It is set and cleared by software..
Allowed values:
0x0: B_0x0: Receiver in active mode permanently
0x1: B_0x1: Receiver can switch between Mute mode and active mode.
Bits 16-20: Driver Enable deassertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). If the USART_TDR register is written during the DEDT time, the new data is transmitted only when the DEDT and DEAT times have both elapsed. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bits 21-25: Driver Enable assertion time This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit time, depending on the oversampling rate). This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Bit 26: Receiver timeout interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the RTOF bit is set in the USART_ISR register.
Bit 27: End of Block interrupt enable This bit is set and cleared by software. Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated when the EOBF flag is set in the USART_ISR register
Bit 28: Word length This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or cleared by software. M[1:0] = '00â: 1 start bit, 8 Data bits, n Stop bit M[1:0] = '01â: 1 start bit, 9 Data bits, n Stop bit M[1:0] = '10â: 1 start bit, 7 Data bits, n Stop bit This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: In 7-bits data length mode, the Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frames detection) are not supported..
Bit 29: FIFO mode enable This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: FIFO mode can be used on standard UART communication, in SPI master/slave mode and in Smartcard modes only. It must not be enabled in IrDA and LIN modes..
Allowed values:
0x0: B_0x0: FIFO mode is disabled.
0x1: B_0x1: FIFO mode is enabled.
Control register 2
Offset: 0x4, reset: 0x0000, access: read-write
19/20 fields covered.
Bit 3: When the DIS_NSS bit is set, the NSS pin input is ignored. Note: When SPI slave mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: SPI slave selection depends on NSS input pin.
0x1: B_0x1: SPI slave is always selected and NSS input pin is ignored.
Bit 4: 7-bit Address Detection/4-bit Address Detection This bit is for selection between 4-bit address detection or 7-bit address detection. This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address (ADD[5:0] and ADD[7:0]) respectively..
Allowed values:
0x0: B_0x0: 4-bit address detection
0x1: B_0x1: 7-bit address detection (in 8-bit data mode)
Bit 5: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: 10-bit break detection
0x1: B_0x1: 11-bit break detection
Bit 6: LIN break detection interrupt enable Break interrupt mask (break detection using break delimiter). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt is inhibited
0x1: B_0x1: An interrupt is generated whenever LBDF = 1 in the USART_ISR register
Bit 8: Last bit clock pulse This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the SCLK pin in synchronous mode. The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit format selected by the M bit in the USART_CR1 register. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The clock pulse of the last data bit is not output to the SCLK pin
0x1: B_0x1: The clock pulse of the last data bit is output to the SCLK pin
Bit 9: Clock phase This bit is used to select the phase of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see and ) This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: The first clock transition is the first data capture edge
0x1: B_0x1: The second clock transition is the first data capture edge
Bit 10: Clock polarity This bit enables the user to select the polarity of the clock output on the SCLK pin in synchronous mode. It works in conjunction with the CPHA bit to produce the desired clock/data relationship This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Steady low value on SCLK pin outside transmission window
0x1: B_0x1: Steady high value on SCLK pin outside transmission window
Bit 11: Clock enable This bit enables the user to enable the SCLK pin. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must be kept at reset value. Refer to . In Smartcard mode, in order to provide correctly the SCLK clock to the smartcard, the steps below must be respected: UE = 0 SCEN = 1 GTPR configuration CLKEN= 1 UE = 1.
Allowed values:
0x0: B_0x0: SCLK pin disabled
0x1: B_0x1: SCLK pin enabled
Bit 14: LIN mode enable This bit is set and cleared by software. The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the SBKRQ bit in the USART_CR1 register, and to detect LIN Sync breaks. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN mode disabled
0x1: B_0x1: LIN mode enabled
Bit 15: Swap TX/RX pins This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX/RX pins are used as defined in standard pinout
0x1: B_0x1: The TX and RX pins functions are swapped. This enables to work in the case of a cross-wired connection to another UART.
Bit 16: RX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the RX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: RX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 17: TX pin active level inversion This bit is set and cleared by software. This enables the use of an external inverter on the TX line. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd = 0/mark)
0x1: B_0x1: TX pin signal values are inverted (VDD =0/mark, Gnd = 1/idle).
Bit 18: Binary data inversion This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Logical data from the data register are send/received in positive/direct logic. (1 = H, 0 = L)
0x1: B_0x1: Logical data from the data register are send/received in negative/inverse logic. (1 = L, 0 = H). The parity bit is also inverted.
Bit 19: Most significant bit first This bit is set and cleared by software. This bitfield can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: data is transmitted/received with data bit 0 first, following the start bit.
0x1: B_0x1: data is transmitted/received with the MSB (bit 7/8) first, following the start bit.
Bit 20: Auto baud rate enable This bit is set and cleared by software. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Auto baud rate detection is disabled.
0x1: B_0x1: Auto baud rate detection is enabled.
Bits 21-22: Auto baud rate mode These bits are set and cleared by software. This bitfield can only be written when ABREN = 0 or the USART is disabled (UEÂ =Â 0). Note: If DATAINVÂ =Â 1 and/or MSBFIRSTÂ =Â 1 the patterns must be the same on the line, for example 0xAA for MSBFIRST) If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Measurement of the start bit is used to detect the baud rate.
0x1: B_0x1: Falling edge to falling edge measurement (the received frame must start with a single bit = 1 and Frame = Start10xxxxxx)
0x2: B_0x2: 0x7F frame detection.
0x3: B_0x3: 0x55 frame detection
Bit 23: Receiver timeout enable This bit is set and cleared by software. When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle (no reception) for the duration programmed in the RTOR (receiver timeout register). Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver timeout feature disabled.
0x1: B_0x1: Receiver timeout feature enabled.
Bits 24-31: Address of the USART node ADD[7:4]: These bits give the address of the USART node or a character code to be recognized. They are used to wake up the MCU with 7-bit address mark detection in multiprocessor communication during Mute mode or low-power mode. The MSB of the character sent by the transmitter should be equal to 1. They can also be used for character detection during normal reception, Mute mode inactive (for example, end of block detection in ModBus protocol). In this case, the whole received character (8-bit) is compared to the ADD[7:0] value and CMF flag is set on match. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0). ADD[3:0]: These bits give the address of the USART node or a character code to be recognized. They are used for wakeup with address mark detection, in multiprocessor communication during Mute mode or low-power mode. These bits can only be written when reception is disabled (RE = 0) or the USART is disabled (UEÂ =Â 0)..
Control register 3
Offset: 0x8, reset: 0x0000, access: read-write
24/24 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
TXFTCFG
rw |
RXFTIE
rw |
RXFTCFG
rw |
TCBGTIE
rw |
TXFTIE
rw |
WUFIE
rw |
WUS
rw |
SCARCNT
rw |
||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
DEP
rw |
DEM
rw |
DDRE
rw |
OVRDIS
rw |
ONEBIT
rw |
CTSIE
rw |
CTSE
rw |
RTSE
rw |
DMAT
rw |
DMAR
rw |
SCEN
rw |
NACK
rw |
HDSEL
rw |
IRLP
rw |
IREN
rw |
EIE
rw |
Bit 0: Error interrupt enable Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing error, overrun error noise flag or SPI slave underrun error (FEÂ =Â 1 or OREÂ =Â 1 or NEÂ =Â 1 or UDR = 1 in the USART_ISR register)..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: interrupt generated when FE = 1 or ORE = 1 or NE = 1 or UDR = 1 (in SPI slave mode) in the USART_ISR register.
Bit 1: IrDA mode enable This bit is set and cleared by software. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: IrDA disabled
0x1: B_0x1: IrDA enabled
Bit 2: IrDA low-power This bit is used for selecting between normal and low-power IrDA modes This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Normal mode
0x1: B_0x1: Low-power mode
Bit 4: Smartcard NACK enable This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: NACK transmission in case of parity error is disabled
0x1: B_0x1: NACK transmission during parity error is enabled
Bit 5: Smartcard mode enable This bit is used for enabling Smartcard mode. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Smartcard Mode disabled
0x1: B_0x1: Smartcard Mode enabled
Bit 8: RTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: RTS hardware flow control disabled
0x1: B_0x1: RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The nRTS output is asserted (pulled to 0) when data can be received.
Bit 9: CTS enable This bit can only be written when the USART is disabled (UEÂ =Â 0) Note: If the hardware flow control feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: CTS hardware flow control disabled
0x1: B_0x1: CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0). If the nCTS input is deasserted while data is being transmitted, then the transmission is completed before stopping. If data is written into the data register while nCTS is asserted, the transmission is postponed until nCTS is asserted.
Bit 11: One sample bit method enable This bit enables the user to select the sample method. When the one sample bit method is selected the noise detection flag (NE) is disabled. This bit can only be written when the USART is disabled (UEÂ =Â 0)..
Allowed values:
0x0: B_0x0: Three sample bit method
0x1: B_0x1: One sample bit method
Bit 12: Overrun Disable This bit is used to disable the receive overrun detection. the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register. When FIFO mode is enabled, the RXFIFO is bypassed and data is written directly in USART_RDR register. Even when FIFO management is enabled, the RXNE flag is to be used. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: This control bit enables checking the communication flow w/o reading the data.
Allowed values:
0x0: B_0x0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
0x1: B_0x1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
Bit 13: DMA Disable on Reception Error This bit can only be written when the USART is disabled (UE=0). Note: The reception errors are: parity error, framing error or noise error..
Allowed values:
0x0: B_0x0: DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred (used for Smartcard mode).
0x1: B_0x1: DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE/RXFNE is case FIFO mode is enabled) before clearing the error flag.
Bit 14: Driver enable mode This bit enables the user to activate the external transceiver control, through the DE signal. This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. ..
Allowed values:
0x0: B_0x0: DE function is disabled.
0x1: B_0x1: DE function is enabled. The DE signal is output on the RTS pin.
Bit 15: Driver enable polarity selection This bit can only be written when the USART is disabled (UEÂ =Â 0). Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: DE signal is active high.
0x1: B_0x1: DE signal is active low.
Bits 17-19: Smartcard auto-retry count This bitfield specifies the number of retries for transmission and reception in Smartcard mode. In transmission mode, it specifies the number of automatic retransmission retries, before generating a transmission error (FE bit set). In reception mode, it specifies the number or erroneous reception trials, before generating a reception error (RXNE/RXFNE and PE bits set). This bitfield must be programmed only when the USART is disabled (UEÂ =Â 0). When the USART is enabled (UEÂ =Â 1), this bitfield may only be written to 0x0, in order to stop retransmission. Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1: B_0x1: number of automatic retransmission attempts (before signaling error)
0x2: B_0x2: number of automatic retransmission attempts (before signaling error)
0x3: B_0x3: number of automatic retransmission attempts (before signaling error)
0x4: B_0x4: number of automatic retransmission attempts (before signaling error)
0x5: B_0x5: number of automatic retransmission attempts (before signaling error)
0x6: B_0x6: number of automatic retransmission attempts (before signaling error)
0x7: B_0x7: number of automatic retransmission attempts (before signaling error)
Bits 20-21: Wakeup from low-power mode interrupt flag selection This bitfield specifies the event which activates the WUF (Wakeup from low-power mode flag). This bitfield can only be written when the USART is disabled (UE = 0). If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: WUF active on address match (as defined by ADD[7:0] and ADDM7)
0x2: B_0x2: WUF active on start bit detection
0x3: B_0x3: WUF active on RXNE/RXFNE.
Bit 22: Wakeup from low-power mode interrupt enable This bit is set and cleared by software. Note: WUFIE must be set before entering in low-power mode. If the USART does not support the wakeup from Stop feature, this bit is reserved and must be kept at reset value. Refer to page 835..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever WUF = 1 in the USART_ISR register
Bit 24: Transmission Complete before guard time, interrupt enable This bit is set and cleared by software. Note: If the USART does not support the Smartcard mode, this bit is reserved and must be kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Interrupt inhibited
0x1: B_0x1: USART interrupt generated whenever TCBGT=1 in the USART_ISR register
Bits 25-27: Receive FIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: Receive FIFO reaches 1/8 of its depth
0x1: B_0x1: Receive FIFO reaches 1/4 of its depth
0x2: B_0x2: Receive FIFO reaches 1/2 of its depth
0x3: B_0x3: Receive FIFO reaches 3/4 of its depth
0x4: B_0x4: Receive FIFO reaches 7/8 of its depth
0x5: B_0x5: Receive FIFO becomes full
Bits 29-31: TXFIFO threshold configuration Remaining combinations: Reserved.
Allowed values:
0x0: B_0x0: TXFIFO reaches 1/8 of its depth
0x1: B_0x1: TXFIFO reaches 1/4 of its depth
0x2: B_0x2: TXFIFO reaches 1/2 of its depth
0x3: B_0x3: TXFIFO reaches 3/4 of its depth
0x4: B_0x4: TXFIFO reaches 7/8 of its depth
0x5: B_0x5: TXFIFO becomes empty
Baud rate register
Offset: 0xc, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BRR
rw |
|||||||||||||||
Guard time and prescaler register
Offset: 0x10, reset: 0x0000, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
GT
rw |
PSC
rw |
||||||||||||||
Bits 0-7: Prescaler value In IrDA low-power and normal IrDA mode: PSC[7:0] = IrDA Normal and Low-Power baud rate PSC[7:0] is used to program the prescaler for dividing the USART source clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): In Smartcard mode: PSC[4:0]Â =Â Prescaler value PSC[4:0] is used to program the prescaler for dividing the USART source clock to provide the Smartcard clock. The value given in the register (5 significant bits) is multiplied by 2 to give the division factor of the source clock frequency: ... 0010Â 0000: Divides the source clock by 32 (IrDA mode) ... 1111Â 1111: Divides the source clock by 255 (IrDA mode) This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: Bits [7:5] must be kept cleared if Smartcard mode is used. This bitfield is reserved and forced by hardware to '0â when the Smartcard and IrDA modes are not supported. Refer to ..
Allowed values:
0x0: B_0x0: Reserved - do not program this value
0x1: B_0x1: Divides the source clock by 1 (IrDA mode) / by 2 (Smarcard mode)
0x2: B_0x2: Divides the source clock by 2 (IrDA mode) / by 4 (Smartcard mode)
0x3: B_0x3: Divides the source clock by 3 (IrDA mode) / by 6 (Smartcard mode)
0x1F: B_0x1F: Divides the source clock by 31 (IrDA mode) / by 62 (Smartcard mode)
Bits 8-15: Guard time value This bitfield is used to program the Guard time value in terms of number of baud clock periods. This is used in Smartcard mode. The Transmission Complete flag is set after this guard time value. This bitfield can only be written when the USART is disabled (UEÂ =Â 0). Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value. Refer to ..
Receiver timeout register
Offset: 0x14, reset: 0x0000, access: read-write
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
BLEN
rw |
RTO
rw |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RTO
rw |
|||||||||||||||
Request register
Offset: 0x18, reset: 0x0000, access: write-only
0/5 fields covered.
Bit 0: Auto baud rate request Writing 1 to this bit resets the ABRF flag in the USART_ISR and requests an automatic baud rate measurement on the next received data frame. Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept at reset value. Refer to ..
Bit 1: Send break request Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available. Note: When the application needs to send the break character following all previously inserted data, including the ones not yet transmitted, the software should wait for the TXE flag assertion before setting the SBKRQ bit..
Bit 4: Transmit data flush request When FIFO mode is disabled, writing '1â to this bit sets the TXE flag. This enables to discard the transmit data. This bit must be used only in Smartcard mode, when data have not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register. If the USART does not support Smartcard mode, this bit is reserved and must be kept at reset value. When FIFO is enabled, TXFRQ bit is set to flush the whole FIFO. This sets the TXFE flag (Transmit FIFO empty, bit 23 in the USART_ISR register). Flushing the Transmit FIFO is supported in both UART and Smartcard modes. Note: In FIFO mode, the TXFNF flag is reset during the flush request until TxFIFO is empty in order to ensure that no data are written in the data register..
Interrupt & status register
Offset: 0x1c, reset: 0x000000C0, access: read-only
24/24 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861)..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNEÂ =Â 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXNEIEÂ =Â 1 or EIE Â =Â 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: Read data register not empty RXNE bit is set by hardware when the content of the USART_RDR shift register has been transferred to the USART_RDR register. It is cleared by reading from the USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is set immediately..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: Transmit data register empty TXE is set by hardware when the content of the USART_TDR register has been transferred into the shift register. It is cleared by writing to the USART_TDR register. The TXE flag can also be set by writing 1 to the TXFRQ in the USART_RQR register, in order to discard the data (only in Smartcard T = 0 mode, in case of transmission failure). An interrupt is generated if the TXEIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data register full
0x1: B_0x1: Data register not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXNE is also set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Interrupt & status register
Offset: 0x1c, reset: 0x008000C0, access: read-only
28/28 fields covered.
Bit 0: Parity error This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by software, writing 1 to the PECF in the USART_ICR register. An interrupt is generated if PEIE = 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No parity error
0x1: B_0x1: Parity error
Bit 1: Framing error This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register. When transmitting data in Smartcard mode, this bit is set when the maximum number of transmit attempts is reached without success (the card NACKs the data frame). An interrupt is generated if EIEÂ =Â 1 in the USART_CR1 register. Note: This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No Framing error is detected
0x1: B_0x1: Framing error or break character is detected
Bit 2: Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NECF bit in the USART_ICR register. Note: This bit does not generate an interrupt as it appears at the same time as the RXFNE bit which itself generates an interrupt. An interrupt is generated when the NE flag is set during multi buffer communication if the EIE bit is set. When the line is noise-free, the NE flag can be disabled by programming the ONEBIT bit to 1 to increase the USART tolerance to deviations (Refer to Tolerance of the USART receiver to clock deviation on page 861). This error is associated with the character in the USART_RDR..
Allowed values:
0x0: B_0x0: No noise is detected
0x1: B_0x1: Noise is detected
Bit 3: Overrun error This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a software, writing 1 to the ORECF, in the USART_ICR register. An interrupt is generated if RXFNEIEÂ =Â 1 or EIE = 1 in the USART_CR1 register. Note: When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIE bit is set. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register..
Allowed values:
0x0: B_0x0: No overrun error
0x1: B_0x1: Overrun error is detected
Bit 4: Idle line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if IDLEIEÂ =Â 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in the USART_ICR register. Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line occurs). If Mute mode is enabled (MMEÂ =Â 1), IDLE is set if the USART is not mute (RWUÂ =Â 0), whatever the Mute mode selected by the WAKE bit. If RWUÂ =Â 1, IDLE is not set..
Allowed values:
0x0: B_0x0: No Idle line is detected
0x1: B_0x1: Idle line is detected
Bit 5: RXFIFO not empty RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be read from the USART_RDR register. Every read operation from the USART_RDR frees a location in the RXFIFO. RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register. An interrupt is generated if RXFNEIEÂ =Â 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: Data is not received
0x1: B_0x1: Received data is ready to be read.
Bit 6: Transmission complete This bit indicates that the last data written in the USART_TDR has been transmitted out of the shift register. It is set by hardware when the transmission of a frame containing data is complete and when TXFE is set. An interrupt is generated if TCIEÂ =Â 1 in the USART_CR1 register. TC bit is is cleared by software, by writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register. Note: If TE bit is reset and no transmission is on going, the TC bit is immediately set..
Allowed values:
0x0: B_0x0: Transmission is not complete
0x1: B_0x1: Transmission is complete
Bit 7: TXFIFO not full TXFNF is set by hardware when TXFIFO is not full meaning that data can be written in the USART_TDR. Every write operation to the USART_TDR places the data in the TXFIFO. This flag remains set until the TXFIFO is full. When the TXFIFO is full, this flag is cleared indicating that data can not be written into the USART_TDR. An interrupt is generated if the TXFNFIE bit =1 in the USART_CR1 register. Note: The TXFNF is kept reset during the flush request until TXFIFO is empty. After sending the flush request (by setting TXFRQ bit), the flag TXFNF should be checked prior to writing in TXFIFO (TXFNF and TXFE are set at the same time). This bit is used during single buffer transmission..
Allowed values:
0x0: B_0x0: Transmit FIFO is full
0x1: B_0x1: Transmit FIFO is not full
Bit 8: LIN break detection flag This bit is set by hardware when the LIN break is detected. It is cleared by software, by writing 1 to the LBDCF in the USART_ICR. An interrupt is generated if LBDIE = 1 in the USART_CR2 register. Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: LIN Break not detected
0x1: B_0x1: LIN break detected
Bit 9: CTS interrupt flag This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It is cleared by software, by writing 1 to the CTSCF bit in the USART_ICR register. An interrupt is generated if CTSIEÂ =Â 1 in the USART_CR3 register. Note: If the hardware flow control feature is not supported, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: No change occurred on the nCTS status line
0x1: B_0x1: A change occurred on the nCTS status line
Bit 11: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register. An interrupt is generated if RTOIEÂ =Â 1 in the USART_CR2 register. In Smartcard mode, the timeout corresponds to the CWT or BWT timings. Note: If a time equal to the value programmed in RTOR register separates 2 characters, RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8, depending on the oversampling method), RTOF flag is set. The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has already elapsed when RE is set, then RTOF is set. If the USART does not support the Receiver timeout feature, this bit is reserved and kept at reset value..
Allowed values:
0x0: B_0x0: Timeout value not reached
0x1: B_0x1: Timeout value reached without any data reception
Bit 12: End of block flag This bit is set by hardware when a complete block has been received (for example TÂ =Â 1 Smartcard mode). The detection is done when the number of received bytes (from the start of the block, including the prologue) is equal or greater than BLEN + 4. An interrupt is generated if the EOBIEÂ =Â 1 in the USART_CR2 register. It is cleared by software, writing 1 to the EOBCF in the USART_ICR register. Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: End of Block not reached
0x1: B_0x1: End of Block (number of characters) reached
Bit 13: SPI slave underrun error flag In slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register. Note: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: No underrun error
0x1: B_0x1: underrun error
Bit 14: Auto baud rate error This bit is set by hardware if the baud rate measurement failed (baud rate out of range or character comparison failed) It is cleared by software, by writing 1 to the ABRRQ bit in the USART_CR3 register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 15: Auto baud rate flag This bit is set by hardware when the automatic baud rate has been set (RXFNE is also set, generating an interrupt if RXFNEIE = 1) or when the auto baud rate operation was completed without success (ABREÂ =Â 1) (ABRE, RXFNE and FE are also set in this case) It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to the ABRRQ in the USART_RQR register. Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept at reset value..
Bit 16: Busy flag This bit is set and reset by hardware. It is active when a communication is ongoing on the RX line (successful start bit detected). It is reset at the end of the reception (successful or not)..
Allowed values:
0x0: B_0x0: USART is idle (no reception)
0x1: B_0x1: Reception on going
Bit 17: Character match flag This bit is set by hardware, when a the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIEÂ =Â 1in the USART_CR1 register..
Allowed values:
0x0: B_0x0: No Character match detected
0x1: B_0x1: Character Match detected
Bit 18: Send break flag This bit indicates that a send break character was requested. It is set by software, by writing 1 to the SBKRQ bit in the USART_CR3 register. It is automatically reset by hardware during the stop bit of break transmission..
Allowed values:
0x0: B_0x0: Break character transmitted
0x1: B_0x1: Break character requested by setting SBKRQ bit in USART_RQR register
Bit 19: Receiver wakeup from Mute mode This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE) is selected by the WAKE bit in the USART_CR1 register. When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the MMRQ bit in the USART_RQR register. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Allowed values:
0x0: B_0x0: Receiver in active mode
0x1: B_0x1: Receiver in Mute mode
Bit 20: Wakeup from low-power mode flag This bit is set by hardware, when a wakeup event is detected. The event is defined by the WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register. An interrupt is generated if WUFIEÂ =Â 1 in the USART_CR3 register. Note: When UESM is cleared, WUF flag is also cleared. If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 21: Transmit enable acknowledge flag This bit is set/reset by hardware, when the Transmit Enable value is taken into account by the USART. It can be used when an idle frame request is generated by writing TEÂ =Â 0, followed by TEÂ =Â 1 in the USART_CR1 register, in order to respect the TEÂ =Â 0 minimum period..
Bit 22: Receive enable acknowledge flag This bit is set/reset by hardware, when the Receive Enable value is taken into account by the USART. It can be used to verify that the USART is ready for reception before entering low-power mode. Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and kept at reset value. Refer to ..
Bit 23: TXFIFO empty This bit is set by hardware when TXFIFO is empty. When the TXFIFO contains at least one data, this flag is cleared. The TXFE flag can also be set by writing 1 to the bit TXFRQ (bit 4) in the USART_RQR register. An interrupt is generated if the TXFEIE bit  = 1 (bit 30) in the USART_CR1 register..
Allowed values:
0x0: B_0x0: TXFIFO not empty.
0x1: B_0x1: TXFIFO empty.
Bit 24: RXFIFO full This bit is set by hardware when the number of received data corresponds to RXFIFO size + 1 (RXFIFO full + 1 data in the USART_RDR register. An interrupt is generated if the RXFFIE bit  = 1 in the USART_CR1 register..
Allowed values:
0x0: B_0x0: RXFIFO not full.
0x1: B_0x1: RXFIFO Full.
Bit 25: Transmission complete before guard time flag This bit is set when the last data written in the USART_TDR has been transmitted correctly out of the shift register. It is set by hardware in Smartcard mode, if the transmission of a frame containing data is complete and if the smartcard did not send back any NACK. An interrupt is generated if TCBGTIE = 1 in the USART_CR3 register. This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or by a write to the USART_TDR register. Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at reset value. If the USART supports the Smartcard mode and the Smartcard mode is enabled, the TCBGT reset value is '1â. Refer to on page 835..
Allowed values:
0x0: B_0x0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card)
0x1: B_0x1: Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card).
Bit 26: RXFIFO threshold flag This bit is set by hardware when the threshold programmed in RXFTCFG in USART_CR3 register is reached. This means that there are (RXFTCFG - 1) data in the Receive FIFO and one data in the USART_RDR register. An interrupt is generated if the RXFTIE bit  = 1 (bit 27) in the USART_CR3 register. Note: When the RXFTCFG threshold is configured to '101â, RXFT flag is set if 16 data are available i.e. 15 data in the RXFIFO and 1 data in the USART_RDR. Consequently, the 17th received data does not cause an overrun error. The overrun error occurs after receiving the 18th data..
Allowed values:
0x0: B_0x0: Receive FIFO does not reach the programmed threshold.
0x1: B_0x1: Receive FIFO reached the programmed threshold.
Bit 27: TXFIFO threshold flag This bit is set by hardware when the TXFIFO reaches the threshold programmed in TXFTCFG of USART_CR3 register i.e. the TXFIFO contains TXFTCFG empty locations. An interrupt is generated if the TXFTIE bit  = 1 (bit 31) in the USART_CR3 register..
Allowed values:
0x0: B_0x0: TXFIFO does not reach the programmed threshold.
0x1: B_0x1: TXFIFO reached the programmed threshold.
Receive data register
Offset: 0x24, reset: 0x0000, access: read-only
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RDR
r |
|||||||||||||||
Transmit data register
Offset: 0x28, reset: 0x0000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TDR
rw |
|||||||||||||||
Prescaler register
Offset: 0x2c, reset: 0x0000, access: read-write
1/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
PRESCALER
rw |
|||||||||||||||
Bits 0-3: Clock prescaler The USART input clock can be divided by a prescaler factor: Remaining combinations: Reserved Note: When PRESCALER is programmed with a value different of the allowed ones, programmed prescaler value is 1011 i.e. input clock divided by 256..
Allowed values:
0x0: B_0x0: input clock not divided
0x1: B_0x1: input clock divided by 2
0x2: B_0x2: input clock divided by 4
0x3: B_0x3: input clock divided by 6
0x4: B_0x4: input clock divided by 8
0x5: B_0x5: input clock divided by 10
0x6: B_0x6: input clock divided by 12
0x7: B_0x7: input clock divided by 16
0x8: B_0x8: input clock divided by 32
0x9: B_0x9: input clock divided by 64
0xA: B_0xA: input clock divided by 128
0xB: B_0xB: input clock divided by 256
0x40005c00: Universal serial bus full-speed host/device interface
50/171 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CHEP0R | ||||||||||||||||||||||||||||||||
| 0x4 | CHEP1R | ||||||||||||||||||||||||||||||||
| 0x8 | CHEP2R | ||||||||||||||||||||||||||||||||
| 0xc | CHEP3R | ||||||||||||||||||||||||||||||||
| 0x10 | CHEP4R | ||||||||||||||||||||||||||||||||
| 0x14 | CHEP5R | ||||||||||||||||||||||||||||||||
| 0x18 | CHEP6R | ||||||||||||||||||||||||||||||||
| 0x1c | CHEP7R | ||||||||||||||||||||||||||||||||
| 0x40 | CNTR | ||||||||||||||||||||||||||||||||
| 0x44 | ISTR | ||||||||||||||||||||||||||||||||
| 0x48 | FNR | ||||||||||||||||||||||||||||||||
| 0x4c | DADDR | ||||||||||||||||||||||||||||||||
| 0x54 | LPMCSR | ||||||||||||||||||||||||||||||||
| 0x58 | BCDR | ||||||||||||||||||||||||||||||||
USB endpoint/channel 0 register
Offset: 0x0, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 1 register
Offset: 0x4, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 2 register
Offset: 0x8, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 3 register
Offset: 0xc, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 4 register
Offset: 0x10, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 5 register
Offset: 0x14, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 6 register
Offset: 0x18, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB endpoint/channel 7 register
Offset: 0x1c, reset: 0x00000000, access: Unspecified
2/15 fields covered.
Bits 0-3: endpoint/channel address Device mode Software must write in this field the 4-bit address used to identify the transactions directed to this endpoint. A value must be written before enabling the corresponding endpoint. Host mode Software must write in this field the 4-bit address used to identify the channel addressed by the host transaction..
Bits 4-5: Status bits, for transmission transfers Device mode These bits contain the information about the endpoint status, listed in . These bits can be toggled by the software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STTX bits to NAK, when a correct transfer has occurred (VTTX=1) corresponding to a IN or SETUP (control only) transaction addressed to this channel/endpoint. It then waits for the software to prepare the next set of data to be transmitted. Double-buffered bulk endpoints implement a special transaction flow control, which controls the status based on buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can only be âVALIDâ or âDISABLEDâ. Therefore, the hardware cannot change the status of the channel/endpoint/channel after a successful transaction. If the software sets the STTX bits to 'STALLâ or 'NAKâ for an Isochronous channel/endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode Same as STRX behaviour but for IN transactions (TBC).
Bit 6: Data Toggle, for transmission transfers If the endpoint/channel is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission. If the endpoint/channel is defined as a control one, hardware sets this bit to 1 at the reception of a SETUP PID addressed to this endpoint. If the endpoint/channel is using the double buffer feature, this bit is used to support packet buffer swapping too (Refer to ) If the endpoint/channel is Isochronous, this bit is used to support packet buffer swapping since no data toggling is used for this sort of endpoints and only DATA0 packet are transmitted (Refer to ). Hardware toggles this bit just after the end of data packet transmission, since no handshake is used for Isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint/channel is not a control one) or to force a specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGTX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can only be toggled by writing 1..
Bit 7: Valid USB transaction transmitted Device mode This bit is set by the hardware when an IN transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in the USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written. Host mode Same of VTRX behaviour but for USB OUT and SETUP transactions..
Bit 8: endpoint/channel kind The meaning of this bit depends on the endpoint/channel type configured by the EP_TYPE bits. summarizes the different meanings. DBL_BUF: This bit is set by the software to enable the double-buffering feature for this bulk endpoint. The usage of double-buffered bulk endpoints is explained in Double-buffered endpoints. STATUS_OUT: This bit is set by the software to indicate that a status out transaction is expected: in this case all OUT transactions containing more than zero data bytes are answered 'STALLâ instead of 'ACKâ. This bit may be used to improve the robustness of the application to protocol errors during control transfers and its usage is intended for control endpoints only. When STATUS_OUT is reset, OUT transactions can have any number of bytes, as required..
Bits 9-10: USB type of transaction These bits configure the behavior of this endpoint/channel as described in endpoint/channel type encoding on page 2001. Channel0/Endpoint0 must always be a control endpoint/channel and each USB function must have at least one control endpoint/channel which has address 0, but there may be other control channels/endpoints if required. Only control channels/endpoints handle SETUP transactions, which are ignored by endpoints of other kinds. SETUP transactions cannot be answered with NAK or STALL. If a control endpoint/channel is defined as NAK, the USB peripheral will not answer, simulating a receive error, in the receive direction when a SETUP transaction is received. If the control endpoint/channel is defined as STALL in the receive direction, then the SETUP packet will be accepted anyway, transferring data and issuing the CTR interrupt. The reception of OUT transactions is handled in the normal way, even if the endpoint/channel is a control one. Bulk and interrupt endpoints have very similar behavior and they differ only in the special feature available using the EPKIND configuration bit. The usage of Isochronous channels/endpoints is explained in transfers.
Bit 11: Setup transaction completed Device mode This bit is read-only and it is set by the hardware when the last completed transaction is a SETUP. This bit changes its value only for control endpoints. It must be examined, in the case of a successful receive transaction (VTRX event), to determine the type of transaction occurred. To protect the interrupt service routine from the changes in SETUP bits due to next incoming tokens, this bit is kept frozen while VTRX bit is at 1; its state changes when VTRX is at 0. This bit is read-only. Host mode This bit is set by the software to send a SETUP transaction on a control endpoint. This bit changes its value only for control endpoints. It is cleared by hardware when the SETUP transaction is acknowledged and VTTX interrupt generated..
Bits 12-13: Status bits, for reception transfers Device mode These bits contain information about the endpoint status, which are listed in Reception status encoding on page 2000.These bits can be toggled by software to initialize their value. When the application software writes '0, the value remains unchanged, while writing '1 makes the bit value toggle. Hardware sets the STRX bits to NAK when a correct transfer has occurred (VTRX=1) corresponding to a OUT or SETUP (control only) transaction addressed to this endpoint, so the software has the time to elaborate the received data before it acknowledge a new transaction Double-buffered bulk endpoints implement a special transaction flow control, which control the status based upon buffer availability condition (Refer to endpoints). If the endpoint is defined as Isochronous, its status can be only âVALIDâ or âDISABLEDâ, so that the hardware cannot change the status of the endpoint after a successful transaction. If the software sets the STRX bits to 'STALLâ or 'NAKâ for an Isochronous endpoint, the USB peripheral behavior is not defined. These bits are read/write but they can be only toggled by writing '1. Host mode These bits are the host application controls to start, retry, or abort host transactions driven by the channel. These bits also contain information about the device answer to the last IN channel transaction and report the current status of the channel according to the following STRX table of states: - DISABLE DISABLE value is reported in case of ACK acknowledge is received on a single-buffer channel. When in DISABLE state the channel is unused or not active waiting for application to restart it by writing VALID. Application can reset a VALID channel to DISABLE to abort a transaction. In this case the transaction is immediately removed from the Host execution list. If the aborted transaction was already under execution it will be regularly terminated on the USB but the relative VTRX interrupt is not generated. - VALID An Host channel is actively trying to submit USB transaction to device only when in VALID state.VALID state can be set by software or automatically by hardware on a NAKED channel at the start of a new frame. When set to VALID, an host channel enters the host execution queue and waits permission from the Host Frame Schedure to submit its configured transaction. VALID value is also reported in case of ACK acknowledge is received on a double-buffered channel. In this case the channel remains active on the alternate buffer while application needs to read the current buffer and toggle DTOGTX. In case software is late in reading and the alternate buffer is not ready, the host channel is automatically suspended transparently to the application. The suspended double buffered channel will be re-activated as soon as delay is recovered and DTOGTX is toggled. - NAK NAK value is reported in case of NAK acknowledge received. When in NAK state the channel is suspended and does not try to transmit. NAK state is moved to VALID by hardware at the start of the next frame, or software can change it to immediately retry transmission by writing it to VALID, or can disable it and abort the transaction by writing DISABLE - STALL STALL value is reported in case of STALL acknowledge received. When in STALL state the channel behaves as disabled. Application should not retry transmission but reset the USB and re-enumerate..
Bit 14: Data Toggle, for reception transfers If the endpoint/channel is not Isochronous, this bit contains the expected value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware toggles this bit, when the ACK handshake is sent following a data packet reception having a matching data PID value; if the endpoint is defined as a control one, hardware clears this bit at the reception of a SETUP PID received from host (in device) or acknowledged by device (in host). If the endpoint/channel is using the double-buffering feature this bit is used to support packet buffer swapping too (Refer to ). If the endpoint/channel is Isochronous, this bit is used only to support packet buffer swapping for data transmission since no data toggling is used for this kind of channels/endpoints and only DATA0 packet are transmitted (Refer to Isochronous transfers). Hardware toggles this bit just after the end of data packet reception, since no handshake is used for isochronous transfers. This bit can also be toggled by the software to initialize its value (mandatory when the endpoint is not a control one) or to force specific data toggle/packet buffer usage. When the application software writes '0, the value of DTOGRX remains unchanged, while writing '1 makes the bit value toggle. This bit is read/write but it can be only toggled by writing 1..
Bit 15: USB valid transaction received Device mode This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated. The type of occurred transaction, OUT or SETUP, can be determined from the SETUP bit described below. A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually transferred, as in the case of protocol errors or data toggle mismatches. This bit is read/write but only '0 can be written, writing 1 has no effect. Host mode This bit is set by the hardware when an IN transaction is successfully completed on this channel. The software can only clear this bit. If the VTRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated. - A transaction ended with a NAK sets this bit and NAK answer is reported to application reading the NAK state from the STRX field of this register. One naked transaction keeps pending and is automatically retried by the Host at the next frame, or the Host can immediately retry by resetting STRX state to VALID. - A transaction ended by STALL handshake sets this bit and the STALL answer is reported to application reading the STALL state from the STRX field of this register. Host application should consequently disable the channel and re-enumerate. - A transaction ended with ACK handshake sets this bit If double buffering is disabled, ACK answer is reported by application reading the DISABLE state from the STRX field of this register. Host application should read received data from USBRAM and re-arm the channel by writing VALID to the STRX field of this register. If double buffering is enabled, ACK answer is reported by application reading VALID state from the STRX field of this register. Host application should read received data from USBRAM and toggle the DTOGTX bit of this register. This bit is read/write but only '0 can be written, writing 1 has no effect..
Bit 25: Transmit error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
Bit 26: Receive error Host mode This bit is set by the hardware when an error (e.g. no answer by the device, CRC error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register is set a generic interrupt condition is generated together with the channel related flag, which is always activated..
USB control register
Offset: 0x40, reset: 0x00000003, access: Unspecified
17/17 fields covered.
Bit 0: USB Reset Device mode Software can set this bit to reset the USB core, exactly as it happens when receiving a RESET signaling on the USB.The USB peripheral, in response to a RESET, resets its internal protocol state machine. Reception and transmission are disabled until the RESET bit is cleared. All configuration registers do not reset: the microcontroller must explicitly clear these registers (this is to ensure that the RESET interrupt can be safely delivered, and any transaction immediately followed by a RESET can be completed). The function address and endpoint registers are reset by an USB reset event. Host mode Software sets this bit to drive USB reset state on the bus and initialize the device. USB reset terminates as soon as this bit is cleared by software..
Allowed values:
0: NoEffect: No effect
1: Reset: USB core is under reset / USB reset driven
Bit 1: Power down This bit is used to completely switch off all USB-related analog parts if it is required to completely disable the USB peripheral for any reason. When this bit is set, the USB peripheral is disconnected from the transceivers and it cannot be used..
Allowed values:
0x0: B_0x0: Exit Power Down.
0x1: B_0x1: Enter Power down mode.
Bit 2: Suspend state effective This bit is set by hardware as soon as the suspend state entered through the SUSPEN control gets internally effective. In this state USB activity is suspended, USB clock is gated, transceiver is set in low power mode by disabling the differential receiver. Only asynchronous wakeup logic and single ended receiver is kept alive to detect remote wakeup or resume events. Software must poll this bit to confirm it to be set before any STOP mode entry. This bit is cleared by hardware simultaneously to the WAKEUP flag being set..
Allowed values:
0x0: B_0x0: Normal operation
0x1: B_0x1: Suspend state
Bit 3: Suspend state enable Device mode Software can set this bit when the SUSP interrupt is received, which is issued when no traffic is received by the USB peripheral for 3Â ms. Software can also set this bit when the L1REQ interrupt is received with positive acknowledge sent. As soon as the suspend state is propagated internally all device activity is stopped, USB clock is gated, USB transceiver is set into low power mode and the SUSPRDY bit is set by hardware. In the case that device application wants to purse more aggressive power saving by stopping the USB clock source and by moving the microcontroller to stop mode, as in the case of bus powered device application, it must first wait few cycles to see the SUSPRDY=1 acknowledge the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set. Host mode Software can set this bit when Host application has nothing scheduled for the next frames and wants to enter long term power saving. When set, it stops immediately SOF generation and any other host activity, gates the USB clock and sets the transceiver in low power mode. If any USB transaction is on-going at the time SUSPEN is set, suspend is entered at the end of the current transaction. As soon as suspend state is propagated internally and gets effective the SUSPRDY bit is set. In the case that host application wants to purse more aggressive power saving by stopping the USB clock source and by moving the micro-controller to STOP mode, it must first wait few cycles to see SUSPRDY=1 acknowledge to the suspend request. This bit is cleared by hardware simultaneous with the WAKEUP flag set..
Allowed values:
0: NoEffect: No effect
1: Suspend: Enter L1/L2 suspend
Bit 4: L2 Remote Wakeup / Resume driver Device mode The microcontroller can set this bit to send remote wake-up signaling to the Host. It must be activated, according to USB specifications, for no less than 1ms and no more than 15ms after which the Host PC is ready to drive the resume sequence up to its end. Host mode Software sets this bit to send resume signaling to the device. Software clears this bit to send end of resume to device and restart SOF generation. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt..
Allowed values:
0x0: B_0x0: No effect
0x1: B_0x1: Send L2 resume signaling to device
Bit 5: L1 Remote Wakeup / Resume driver Device mode Software sets this bit to send a LPM L1 50us remote wakeup signaling to the host. After the signaling ends, this bit is cleared by hardware. Host mode Software sets this bit to send L1 resume signaling to device. Resume duration and next SOF generation is automatically driven to set the restart of USB activity timely aligned with the programmed BESL value. In the context of remote wake up, this bit is to be set following the WAKEUP interrupt. This bit is cleared by hardware at the end of resume..
Allowed values:
0: NoEffect: No effect
1: WakeupResume: Send 50us remote-wakeup signaling to host / Send L1 resume signaling to device
USB interrupt status register
Offset: 0x44, reset: 0x00000000, access: Unspecified
5/14 fields covered.
Bits 0-3: Device Endpoint / Host channel identification number These bits are written by the hardware according to the host channel or device endpoint number, which generated the interrupt request. If several endpoint/channel transactions are pending, the hardware writes the identification number related to the endpoint/channel having the highest priority defined in the following way: Two levels are defined, in order of priority: Isochronous and double-buffered bulk channels/endpoints are considered first and then the others are examined. If more than one endpoint/channel from the same set is requesting an interrupt, the IDN bits in USB_ISTR register are assigned according to the lowest requesting register, CHEP0R having the highest priority followed by CHEP1R and so on. The application software can assign a register to each endpoint/channel according to this priority scheme, so as to order the concurring endpoint/channel requests in a suitable way. These bits are read only..
Bit 4: Direction of transaction This bit is written by the hardware according to the direction of the successful transaction, which generated the interrupt request. If DIR bit=0, VTTX bit is set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of IN type (data transmitted by the USB peripheral to the host PC). If DIR bit=1, VTRX bit or both VTTX/VTRX are set in the USB_EPnR register related to the interrupting endpoint. The interrupting transaction is of OUT type (data received by the USB peripheral from the host PC) or two pending transactions are waiting to be processed. This information can be used by the application software to access the USB_EPnR bits related to the triggering transaction since it represents the direction having the interrupt pending. This bit is read-only..
Bit 8: Expected start of frame This bit is set by the hardware when an SOF packet is expected but not received. The host sends an SOF packet each 1Â ms, but if the device does not receive it properly, the Suspend Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is generated. This bit is set even when the missing SOF packets occur while the Suspend Timer is not yet locked. This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 9: Start of frame This bit signals the beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus. The interrupt service routine may monitor the SOF events to have a 1Â ms synchronization event to the USB host and to safely read the USB_FNR register which is updated at the SOF packet reception (this could be useful for isochronous applications). This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 10: USB reset request Device mode This bit is set by hardware when an USB reset is released by the host and the bus returns to idle. USB reset state is internally detected after the sampling of 60 consecutive SE0 cycles. Host mode This bit is set by hardware when device connection or device disconnection is detected. Device connection is signaled after J state is sampled for 22cycles consecutively from unconnected state. Device disconnection is signaled after SE0 state is sampled for 22cycles consecutively from connected state..
Bit 11: Suspend mode request This bit is set by the hardware when no traffic has been received for 3Â ms, indicating a suspend mode request from the USB bus. The suspend condition check is enabled immediately after any USB reset and it is disabled by the hardware when the suspend mode is active (SUSPEN=1) until the end of resume sequence. This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 12: Wakeup This bit is set to 1 by the hardware when, during suspend mode, activity is detected that wakes up the USB peripheral. This event asynchronously clears the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line, which can be used to notify the rest of the device (e.g. wakeup unit) about the start of the resume process. This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 13: Error This flag is set whenever one of the errors listed below has occurred: NANS: No ANSwer. The timeout for a host response has expired. CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or in the data, was wrong. BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data, and/or CRC. FVIO: Framing format Violation. A non-standard frame was received (EOP not in the right place, wrong token sequence, etc.). The USB software can usually ignore errors, since the USB peripheral and the PC host manage retransmission in case of errors in a fully transparent way. This interrupt can be useful during the software development phase, or to monitor the quality of transmission over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy environment, broken conductor in the USB cable and so on). This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 14: Packet memory area over / underrun This bit is set if the microcontroller has not been able to respond in time to an USB memory request. The USB peripheral handles this event in the following way: During reception an ACK handshake packet is not sent, during transmission a bit-stuff error is forced on the transmitted stream; in both cases the host will retry the transaction. The PMAOVR interrupt should never occur during normal operations. Since the failed transaction is retried by the host, the application software has the chance to speed-up device operations during this interrupt handling, to be ready for the next transaction retry; however this does not happen during Isochronous transfers (no isochronous transaction is anyway retried) leading to a loss of data in this case. This bit is read/write but only '0 can be written and writing '1 has no effect..
Bit 16: 512 byte threshold interrupt This bit is set to 1 by the hardware when 512 bytes have been transmitted or received during isochronous transfers. This bit is read/write but only 0 can be written and writing 1 has no effect. Note that no information is available to indicate the associated channel/endpoint, however in practice only one ISO endpoint/channel with such large packets can be supported, so that channel..
Bit 29: Device connection status Host mode: This bit contains information about device connection status. It is set by hardware when a LS/FS device is attached to the host while it is reset when the device is disconnected..
Allowed values:
0x0: B_0x0: No device connected
0x1: B_0x1: FS or LS device connected to the host
USB frame number register
Offset: 0x48, reset: 0x00000000, access: Unspecified
5/5 fields covered.
Bit 13: Locked Device mode This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence. Once locked, the frame timer remains in this state until an USB reset or USB suspend event occurs..
USB device address
Offset: 0x4c, reset: 0x00000000, access: Unspecified
0/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EF
rw |
ADD
rw |
||||||||||||||
Bits 0-6: Device address Device mode These bits contain the USB function address assigned by the host PC during the enumeration process. Both this field and the endpoint/channel Address (EA) field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint. Host mode These bits contain the address transmitted with the LPM transaction.
LPM control and status register
Offset: 0x54, reset: 0x00000000, access: Unspecified
3/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
BESL
r |
REMWAKE
r |
LPMACK
rw |
LPMEN
rw |
||||||||||||
Bit 0: LPM support enable Device mode This bit is set by the software to enable the LPM support within the USB device. If this bit is at '0 no LPM transactions are handled. Host mode Software sets this bit to transmit an LPM transaction to device. This bit is cleared by hardware, simultaneous with L1REQ flag set, when device answer is received.
Bit 1: LPM Token acknowledge enable The NYET/ACK will be returned only on a successful LPM transaction: No errors in both the EXT token and the LPM token (else ERROR) A valid bLinkState = 0001B (L1) is received (else STALL) This bit contains the device answer to the LPM transaction. It mast be evaluated following the L1REQ interrupt..
Allowed values:
0: Nyet: The valid LPM Token will be NYET / NYET answer
1: Ack: The valid LPM Token will be ACK / ACK answer
Battery charging detector
Offset: 0x58, reset: 0x00000000, access: Unspecified
4/9 fields covered.
Bit 0: Battery charging detector (BCD) enable Device mode This bit is set by the software to enable the BCD support within the USB device. When enabled, the USB PHY is fully controlled by BCD and cannot be used for normal communication. Once the BCD discovery is finished, the BCD should be placed in OFF mode by clearing this bit to '0 in order to allow the normal USB operation..
Bit 7: DM pull-up detection status Device mode This bit is active only during PD and gives the result of comparison between DM voltage level and VLGC threshold. In normal situation, the DM level should be below this threshold. If it is above, it means that the DM is externally pulled high. This can be caused by connection to a PS2 port (which pulls-up both DP and DM lines) or to some proprietary charger not following the BCD specification..
Allowed values:
0x0: B_0x0: Normal port detected (connected to SDP, ACA, CDP or DCP).
0x1: B_0x1: PS2 port or proprietary charger detected.
Bit 15: DP pull-up / DPDM pull-down Device mode This bit is set by software to enable the embedded pull-up on DP line. Clearing it to '0 can be used to signal disconnect to the host when needed by the user software. Host mode This bit is set by software to enable the embedded pull-down on DP and DM lines..
0x40010030: System configuration controller
4/5 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CSR | ||||||||||||||||||||||||||||||||
| 0x4 | CCR | ||||||||||||||||||||||||||||||||
VREFBUF control and status register
Offset: 0x0, reset: 0x00000002, access: Unspecified
4/4 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
VRR
r |
VRS
rw |
HIZ
rw |
ENVR
rw |
||||||||||||
Bit 0: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode..
Allowed values:
0x0: B_0x0: Internal voltage reference mode disable (external voltage reference mode).
0x1: B_0x1: Internal voltage reference mode (reference buffer enable or hold mode) enable.
Bit 1: High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration..
Allowed values:
0x0: B_0x0: VREF+ pin is internally connected to the voltage reference buffer output.
0x1: B_0x1: VREF+ pin is high impedance.
VREFBUF calibration control register
Offset: 0x4, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
TRIM
rw |
|||||||||||||||
0x40002c00: System window watchdog
2/6 fields covered. Toggle Registers
| Offset | Name | 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x0 | CR | ||||||||||||||||||||||||||||||||
| 0x4 | CFR | ||||||||||||||||||||||||||||||||
| 0x8 | SR | ||||||||||||||||||||||||||||||||
Control register
Offset: 0x0, reset: 0x0000007F, access: read-write
1/2 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDGA
rw |
T
rw |
||||||||||||||
Configuration register
Offset: 0x4, reset: 0x0000007F, access: read-write
1/3 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
WDGTB
rw |
EWI
rw |
W
rw |
|||||||||||||
Bits 11-13: Timer base The timebase of the prescaler can be modified as follows:.
Allowed values:
0x0: B_0x0: CK Counter Clock (PCLK div 4096) div 1
0x1: B_0x1: CK Counter Clock (PCLK div 4096) div 2
0x2: B_0x2: CK Counter Clock (PCLK div 4096) div 4
0x3: B_0x3: CK Counter Clock (PCLK div 4096) div 8
0x4: B_0x4: CK Counter Clock (PCLK div 4096) div 16
0x5: B_0x5: CK Counter Clock (PCLK div 4096) div 32
0x6: B_0x6: CK Counter Clock (PCLK div 4096) div 64
0x7: B_0x7: CK Counter Clock (PCLK div 4096) div 128
Status register
Offset: 0x8, reset: 0x00000000, access: read-write
0/1 fields covered.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
EWIF
rw |
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