ADRDY

Bit 0: ADC ready This bit is set by hardware after the ADC has been enabled (ADENÂ =Â 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it..

Allowed values:
0x0: B_0x0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: ADC is ready to start conversion

EOSMP

Bit 1: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to '1’..

Allowed values:
0x0: B_0x0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: End of sampling phase reached

EOC

Bit 2: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register..

Allowed values:
0x0: B_0x0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Channel conversion complete

EOS

Bit 3: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it..

Allowed values:
0x0: B_0x0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Conversion sequence complete

OVR

Bit 4: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it..

Allowed values:
0x0: B_0x0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Overrun has occurred

AWD1

Bit 7: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR1 and ADC_HR1 registers. It is cleared by software by programming it to 1..

Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred

AWD2

Bit 8: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD2TR and ADC_AWD2TR registers. It is cleared by software programming it it..

Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred

AWD3

Bit 9: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in ADC_AWD3TR and ADC_AWD3TR registers. It is cleared by software by programming it to 1..

Allowed values:
0x0: B_0x0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)
0x1: B_0x1: Analog watchdog event occurred

EOCAL

Bit 11: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it..

Allowed values:
0x0: B_0x0: Calibration is not complete
0x1: B_0x1: Calibration is complete

CCRDY

Bit 13: Channel Configuration Ready flag This flag bit is set by hardware when the channel configuration is applied after programming to ADC_CHSELR register or changing CHSELRMOD or SCANDIR. It is cleared by software by programming it to it. Note: When the software configures the channels (by programming ADC_CHSELR or changing CHSELRMOD or SCANDIR), it must wait until the CCRDY flag rises before configuring again or starting conversions, otherwise the new configuration (or the START bit) is ignored. Once the flag is asserted, if the software needs to configure again the channels, it must clear the CCRDY flag before proceeding with a new configuration..

Allowed values:
0x0: B_0x0: Channel configuration update not applied.
0x1: B_0x1: Channel configuration update is applied.

ADRDYIE

Bit 0: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADRDY interrupt disabled.
0x1: B_0x1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

EOSMPIE

Bit 1: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: EOSMP interrupt disabled.
0x1: B_0x1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

EOCIE

Bit 2: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: EOC interrupt disabled
0x1: B_0x1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

EOSIE

Bit 3: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: EOS interrupt disabled
0x1: B_0x1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

OVRIE

Bit 4: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Overrun interrupt disabled
0x1: B_0x1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

AWD1IE

Bit 7: Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled

AWD2IE

Bit 8: Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled

AWD3IE

Bit 9: Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. Note: The Software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Analog watchdog interrupt disabled
0x1: B_0x1: Analog watchdog interrupt enabled

EOCALIE

Bit 11: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: End of calibration interrupt disabled
0x1: B_0x1: End of calibration interrupt enabled

CCRDYIE

Bit 13: Channel Configuration Ready Interrupt enable This bit is set and cleared by software to enable/disable the channel configuration ready interrupt. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Channel configuration ready interrupt disabled
0x1: B_0x1: Channel configuration ready interrupt enabled

ADEN

Bit 0: ADC enable command This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCALÂ =Â 0, ADSTPÂ =Â 0, ADSTARTÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0).

Allowed values:
0x0: B_0x0: ADC is disabled (OFF state)
0x1: B_0x1: Write 1 to enable the ADC.

ADDIS

Bit 1: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: Setting ADDIS to '1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing).

Allowed values:
0x0: B_0x0: No ADDIS command ongoing
0x1: B_0x1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

ADSTART

Bit 2: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: In single conversion mode (CONTÂ =Â 0, DISCENÂ =Â 0), when software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion Sequence (EOS) flag. In discontinuous conversion mode(CONTÂ =Â 0, DISCENÂ =Â 1), when the software trigger is selected (EXTENÂ =Â 00): at the assertion of the end of Conversion (EOC) flag. In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. Note: The software is allowed to set ADSTART only when ADENÂ =Â 1 and ADDISÂ =Â 0 (ADC is enabled and there is no pending request to disable the ADC). After writing to ADC_CHSELR register or changing CHSELRMOD or SCANDIRW, it is mandatory to wait until CCRDY flag is asserted before setting ADSTART, otherwise, the value written to ADSTART is ignored..

Allowed values:
0x0: B_0x0: No ADC conversion is ongoing.
0x1: B_0x1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

ADSTP

Bit 4: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. Note: Setting ADSTP to '1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC).

Allowed values:
0x0: B_0x0: No ADC stop conversion command ongoing
0x1: B_0x1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

ADVREGEN

Bit 28: ADC Voltage Regulator Enable This bit is set by software, to enable the ADC internal voltage regulator. The voltage regulator output is available after tADCVREG_SETUP. It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is et to 0. Note: The software is allowed to program this bit field only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..

Allowed values:
0x0: B_0x0: ADC voltage regulator disabled
0x1: B_0x1: ADC voltage regulator enabled

ADCAL

Bit 31: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0). The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADENÂ =Â 1 and ADSTARTÂ =Â 0 (ADC enabled and no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Calibration complete
0x1: B_0x1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

DMAEN

Bit 0: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to . Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: DMA disabled
0x1: B_0x1: DMA enabled

DMACFG

Bit 1: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to page 403 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: DMA one shot mode selected
0x1: B_0x1: DMA circular mode selected

SCANDIR

Bit 2: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence. It is effective only if CHSELMOD bit is cleared to 0. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Upward scan (from CHSEL0 to CHSEL18)
0x1: B_0x1: Backward scan (from CHSEL18 to CHSEL0)

RES

Bits 3-4: Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADENÂ =Â 0..

Allowed values:
0x0: B_0x0: 12 bits
0x1: B_0x1: 10 bits
0x2: B_0x2: 8 bits
0x3: B_0x3: 6 bits

ALIGN

Bit 5: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Data alignment and resolution (oversampling disabled: OVSE = 0) on page 401 Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Right alignment
0x1: B_0x1: Left alignment

EXTSEL

Bits 6-8: External trigger selection These bits select the external event used to trigger the start of conversion (refer to External triggers for details): Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: TRG0
0x1: B_0x1: TRG1
0x2: B_0x2: TRG2
0x3: B_0x3: TRG3
0x4: B_0x4: TRG4
0x5: B_0x5: TRG5
0x6: B_0x6: TRG6
0x7: B_0x7: TRG7

EXTEN

Bits 10-11: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Hardware trigger detection disabled (conversions can be started by software)
0x1: B_0x1: Hardware trigger detection on the rising edge
0x2: B_0x2: Hardware trigger detection on the falling edge
0x3: B_0x3: Hardware trigger detection on both the rising and falling edges

OVRMOD

Bit 12: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC_DR register is preserved with the old data when an overrun is detected.
0x1: B_0x1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

CONT

Bit 13: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Single conversion mode
0x1: B_0x1: Continuous conversion mode

WAIT

Bit 14: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Wait conversion mode off
0x1: B_0x1: Wait conversion mode on

AUTOFF

Bit 15: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Auto-off mode disabled
0x1: B_0x1: Auto-off mode enabled

DISCEN

Bit 16: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCENÂ =Â 1 and CONTÂ =Â 1. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Discontinuous mode disabled
0x1: B_0x1: Discontinuous mode enabled

CHSELRMOD

Bit 21: Mode selection of the ADC_CHSELR register This bit is set and cleared by software to control the ADC_CHSELR feature: Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Each bit of the ADC_CHSELR register enables an input
0x1: B_0x1: ADC_CHSELR register is able to sequence up to 8 channels

AWD1SGL

Bit 22: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Analog watchdog 1 enabled on all channels
0x1: B_0x1: Analog watchdog 1 enabled on a single channel

AWD1EN

Bit 23: Analog watchdog enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Analog watchdog 1 disabled
0x1: B_0x1: Analog watchdog 1 enabled

AWD1CH

Bits 26-30: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register. The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog input Channel 0 monitored by AWD
0x1: B_0x1: ADC analog input Channel 1 monitored by AWD
0x11: B_0x11: ADC analog input Channel 17 monitored by AWD
0x12: B_0x12: ADC analog input Channel 18 monitored by AWD

OVSE

Bit 0: Oversampler Enable This bit is set and cleared by software. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Oversampler disabled
0x1: B_0x1: Oversampler enabled

OVSR

Bits 2-4: Oversampling ratio This bit filed defines the number of oversampling ratio. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: 2x
0x1: B_0x1: 4x
0x2: B_0x2: 8x
0x3: B_0x3: 16x
0x4: B_0x4: 32x
0x5: B_0x5: 64x
0x6: B_0x6: 128x
0x7: B_0x7: 256x

OVSS

Bits 5-8: Oversampling shift This bit is set and cleared by software. Others: Reserved Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: No shift
0x1: B_0x1: Shift 1-bit
0x2: B_0x2: Shift 2-bits
0x3: B_0x3: Shift 3-bits
0x4: B_0x4: Shift 4-bits
0x5: B_0x5: Shift 5-bits
0x6: B_0x6: Shift 6-bits
0x7: B_0x7: Shift 7-bits
0x8: B_0x8: Shift 8-bits

TOVS

Bit 9: Triggered Oversampling This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: All oversampled conversions for a channel are done consecutively after a trigger
0x1: B_0x1: Each oversampled conversion for a channel needs a trigger

LFTRIG

Bit 29: Low frequency trigger mode enable This bit is set and cleared by software. Note: The software is allowed to write this bit only when ADSTART bit is cleared to 0 (this ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Low Frequency Trigger Mode disabled
0x1: B_0x1: Low Frequency Trigger Mode enabled

CKMODE

Bits 30-31: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..

Allowed values:
0x0: B_0x0: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
0x1: B_0x1: PCLK/2 (Synchronous clock mode)
0x2: B_0x2: PCLK/4 (Synchronous clock mode)
0x3: B_0x3: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle)

SMP1

Bits 0-2: Sampling time selection 1 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: 1.5 ADC clock cycles
0x1: B_0x1: 3.5 ADC clock cycles
0x2: B_0x2: 7.5 ADC clock cycles
0x3: B_0x3: 12.5 ADC clock cycles
0x4: B_0x4: 19.5 ADC clock cycles
0x5: B_0x5: 39.5 ADC clock cycles
0x6: B_0x6: 79.5 ADC clock cycles
0x7: B_0x7: 160.5 ADC clock cycles

SMP2

Bits 4-6: Sampling time selection 2 These bits are written by software to select the sampling time that applies to all channels. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: 1.5 ADC clock cycles
0x1: B_0x1: 3.5 ADC clock cycles
0x2: B_0x2: 7.5 ADC clock cycles
0x3: B_0x3: 12.5 ADC clock cycles
0x4: B_0x4: 19.5 ADC clock cycles
0x5: B_0x5: 39.5 ADC clock cycles
0x6: B_0x6: 79.5 ADC clock cycles
0x7: B_0x7: 160.5 ADC clock cycles

SMPSEL0

Bit 8: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL1

Bit 9: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL2

Bit 10: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL3

Bit 11: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL4

Bit 12: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL5

Bit 13: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL6

Bit 14: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL7

Bit 15: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL8

Bit 16: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL9

Bit 17: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL10

Bit 18: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL11

Bit 19: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL12

Bit 20: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL13

Bit 21: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL14

Bit 22: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL15

Bit 23: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL16

Bit 24: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL17

Bit 25: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

SMPSEL18

Bit 26: Channel-x sampling time selection These bits are written by software to define which sampling time is used. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Sampling time of CHANNELx use the setting of SMP1[2:0] register.
0x1: B_0x1: Sampling time of CHANNELx use the setting of SMP2[2:0] register.

LT1

Bits 0-11: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

HT1

Bits 16-27: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

LT2

Bits 0-11: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

HT2

Bits 16-27: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

CHSEL0

Bit 0: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL1

Bit 1: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL2

Bit 2: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL3

Bit 3: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL4

Bit 4: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL5

Bit 5: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL6

Bit 6: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL7

Bit 7: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL8

Bit 8: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL9

Bit 9: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL10

Bit 10: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL11

Bit 11: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL12

Bit 12: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL13

Bit 13: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL14

Bit 14: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL15

Bit 15: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL16

Bit 16: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL17

Bit 17: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

CHSEL18

Bit 18: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing). If CCRDY is not yet asserted after channel configuration (writing ADC_CHSELR register or changing CHSELRMOD or SCANDIR), the value written to this bit is ignored..

Allowed values:
0x0: B_0x0: Input Channel-x is not selected for conversion
0x1: B_0x1: Input Channel-x is selected for conversion

SQ1

Bits 0-3: 1st conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ2

Bits 4-7: 2nd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ3

Bits 8-11: 3rd conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ4

Bits 12-15: 4th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ5

Bits 16-19: 5th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ6

Bits 20-23: 6th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ7

Bits 24-27: 7th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. Refer to SQ8[3:0] for a definition of channel selection. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

SQ8

Bits 28-31: 8th conversion of the sequence These bits are programmed by software with the channel number (0...14) assigned to the 8th conversion of the sequence. 0b1111 indicates the end of the sequence. When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are ignored. ... Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: CH0
0x1: B_0x1: CH1
0xC: B_0xC: CH12
0xD: B_0xD: CH13
0xE: B_0xE: CH14
0xF: B_0xF: No channel selected (End of sequence)

LT3

Bits 0-11: Analog watchdog 3lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

HT3

Bits 16-27: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to ADC_AWDxTR) on page 407..

DATA

Bits 0-15: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in OVSE = 0) on page 401. Just after a calibration is complete, DATA[6:0] contains the calibration factor..

AWD2CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD2CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 2 (AWD2). Note: The channels selected through ADC_AWD2CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD2
0x1: B_0x1: ADC analog channel-x is monitored by AWD2

AWD3CH0

Bit 0: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH1

Bit 1: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH2

Bit 2: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH3

Bit 3: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH4

Bit 4: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH5

Bit 5: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH6

Bit 6: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH7

Bit 7: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH8

Bit 8: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH9

Bit 9: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH10

Bit 10: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH11

Bit 11: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH12

Bit 12: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH13

Bit 13: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH14

Bit 14: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH15

Bit 15: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH16

Bit 16: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH17

Bit 17: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

AWD3CH18

Bit 18: Analog watchdog channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by analog watchdog 3 (AWD3). Note: The channels selected through ADC_AWD3CR must be also configured into the ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: ADC analog channel-x is not monitored by AWD3
0x1: B_0x1: ADC analog channel-x is monitored by AWD3

CALFACT

Bits 0-6: Calibration factor These bits are written by hardware or by software. Once a calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new calibration is launched. Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software can write these bits only when ADEN=1 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). Refer to SQ8[3:0] for a definition of channel selection..

PRESC

Bits 18-21: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. Other: Reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCALÂ =Â 0, ADSTARTÂ =Â 0, ADSTPÂ =Â 0, ADDISÂ =Â 0 and ADENÂ =Â 0)..

Allowed values:
0x0: B_0x0: input ADC clock not divided
0x1: B_0x1: input ADC clock divided by 2
0x2: B_0x2: input ADC clock divided by 4
0x3: B_0x3: input ADC clock divided by 6
0x4: B_0x4: input ADC clock divided by 8
0x5: B_0x5: input ADC clock divided by 10
0x6: B_0x6: input ADC clock divided by 12
0x7: B_0x7: input ADC clock divided by 16
0x8: B_0x8: input ADC clock divided by 32
0x9: B_0x9: input ADC clock divided by 64
0xA: B_0xA: input ADC clock divided by 128
0xB: B_0xB: input ADC clock divided by 256

VREFEN

Bit 22: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: VREFINT disabled
0x1: B_0x1: VREFINT enabled

TSEN

Bit 23: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. Note: Software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing)..

Allowed values:
0x0: B_0x0: Temperature sensor disabled, DAC_OUT1 connected to ADC channel 12
0x1: B_0x1: Temperature sensor enabled

VBATEN

Bit 24: VBAT enable This bit is set and cleared by software to enable/disable the VBAT channel. Note: The software is allowed to write this bit only when ADSTARTÂ =Â 0 (which ensures that no conversion is ongoing).

Allowed values:
0x0: B_0x0: VBAT channel disabled, DAC_OUT2 connected to ADC channel 14
0x1: B_0x1: VBAT channel enabled

EN

Bit 0: Comparator 1 enable bit This bit is controlled by software (if not locked). It enables the comparator 1:.

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

INMSEL

Bits 4-7: Comparator 1 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM of the comparator 1: > 1000: 1/4 VREFINT.

Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB1
0x7: B_0x7: PC4
0x8: B_0x8: PA0

INPSEL

Bits 8-9: Comparator 1 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP1_INP of the comparator 1 (also see the WINMODE bit):.

Allowed values:
0x0: B_0x0: PC5
0x1: B_0x1: PB2
0x2: B_0x2: PA1
0x3: B_0x3: None (open)

WINMODE

Bit 11: Comparator 1 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1:.

Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 64)

WINOUT

Bit 14: Comparator 1 output selector This bit is controlled by software (if not locked). It selects the comparator 1 output:.

Allowed values:
0x0: B_0x0: COMP1_VALUE
0x1: B_0x1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 64)

POLARITY

Bit 15: Comparator 1 polarity selector This bit is controlled by software (if not locked). It selects the comparator 1 output polarity:.

Allowed values:
0x0: B_0x0: Non-inverted
0x1: B_0x1: Inverted

HYST

Bits 16-17: Comparator 1 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1:.

Allowed values:
0x0: B_0x0: None
0x1: B_0x1: Low
0x2: B_0x2: Medium
0x3: B_0x3: High

PWRMODE

Bits 18-19: Comparator 1 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1: others: Reserved.

Allowed values:
0x0: B_0x0: High speed
0x1: B_0x1: Medium speed

BLANKSEL

Bits 20-24: Comparator 1 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: xxxx1: TIM1 OC4 xxx1x: TIM1 OC5 xx1xx: TIM2 OC3 x1xxx: TIM3 OC3 1xxxx: TIM15 OC2.

Allowed values:
0x0: B_0x0: None (no blanking)

VALUE

Bit 30: Comparator 1 output status This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in ..

LOCK

Bit 31: COMP1_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 1 control register COMP1_CSR[31:0]:.

Allowed values:
0x0: B_0x0: COMP1_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP1_CSR[31:0] register bits can be read but not written by software

EN

Bit 0: Comparator 2 enable bit This bit is controlled by software (if not locked). It enables the comparator 2:.

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

INMSEL

Bits 4-7: Comparator 2 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP2_INM of the comparator 2: > 1000: 1/4 VREFINT.

Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB3
0x7: B_0x7: PB7
0x8: B_0x8: PA2

INPSEL

Bits 8-9: Comparator 2 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP2_INP of the comparator 2 (also see the WINMODE bit):.

Allowed values:
0x0: B_0x0: PB4
0x1: B_0x1: PB6
0x2: B_0x2: PA3
0x3: B_0x3: None (open)

WINMODE

Bit 11: Comparator 2 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP2_INP input of the comparator 2:.

Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 64)

WINOUT

Bit 14: Comparator 2 output selector This bit is controlled by software (if not locked). It selects the comparator 2 output:.

Allowed values:
0x0: B_0x0: COMP2_VALUE
0x1: B_0x1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 64)

POLARITY

Bit 15: Comparator 2 polarity selector This bit is controlled by software (if not locked). It selects the comparator 2 output polarity:.

Allowed values:
0x0: B_0x0: Non-inverted
0x1: B_0x1: Inverted

HYST

Bits 16-17: Comparator 2 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2:.

Allowed values:
0x0: B_0x0: None
0x1: B_0x1: Low
0x2: B_0x2: Medium
0x3: B_0x3: High

PWRMODE

Bits 18-19: Comparator 2 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2: others: Reserved.

Allowed values:
0x0: B_0x0: High speed
0x1: B_0x1: Medium speed

BLANKSEL

Bits 20-24: Comparator 2 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: xxxx1: TIM1 OC4 xxx1x: TIM1 OC5 xx1xx: TIM2 OC3 x1xxx: TIM3 OC3 1xxxx: TIM15 OC2.

Allowed values:
0x0: B_0x0: None (no blanking)

VALUE

Bit 30: Comparator 2 output status This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in ..

LOCK

Bit 31: COMP2_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 2 control register COMP2_CSR[31:0]:.

Allowed values:
0x0: B_0x0: COMP2_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP2_CSR[31:0] register bits can be read but not written by software

EN

Bit 0: Comparator 3 enable bit This bit is controlled by software (if not locked). It enables the comparator 3:.

Allowed values:
0x0: B_0x0: Disable
0x1: B_0x1: Enable

INMSEL

Bits 4-7: Comparator 3 signal selector for inverting input INM This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP3_INM of the comparator 3: > 1000: 1/4 VREFINT.

Allowed values:
0x0: B_0x0: 1/4 VREFINT
0x1: B_0x1: 1/2 VREFINT
0x2: B_0x2: 3/4 VREFINT
0x3: B_0x3: VREFINT
0x4: B_0x4: DAC channel 1
0x5: B_0x5: DAC channel 2
0x6: B_0x6: PB3
0x7: B_0x7: PB7
0x8: B_0x8: PA2

INPSEL

Bits 8-9: Comparator 3 signal selector for non-inverting input This bitfield is controlled by software (if not locked). It selects the signal for the non-inverting input COMP3_INP of the comparator 3 (also see the WINMODE bit):.

Allowed values:
0x0: B_0x0: PB4
0x1: B_0x1: PB6
0x2: B_0x2: PA3
0x3: B_0x3: None (open)

WINMODE

Bit 11: Comparator 3 non-inverting input selector for window mode This bit is controlled by software (if not locked). It selects the signal for COMP3_INP input of the comparator 3:.

Allowed values:
0x0: B_0x0: Signal selected with INPSEL[1:0] bitfield of this register
0x1: B_0x1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 64)

WINOUT

Bit 14: Comparator 3 output selector This bit is controlled by software (if not locked). It selects the comparator 3 output:.

Allowed values:
0x0: B_0x0: COMP2_VALUE
0x1: B_0x1: COMP1_VALUE XOR COMP3_VALUE (required for window mode, see Figure 64)

POLARITY

Bit 15: Comparator 2 polarity selector This bit is controlled by software (if not locked). It selects the comparator 3 output polarity:.

Allowed values:
0x0: B_0x0: Non-inverted
0x1: B_0x1: Inverted

HYST

Bits 16-17: Comparator 3 hysteresis selector This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 3:.

Allowed values:
0x0: B_0x0: None
0x1: B_0x1: Low
0x2: B_0x2: Medium
0x3: B_0x3: High

PWRMODE

Bits 18-19: Comparator 3 power mode selector This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 3: others: Reserved.

Allowed values:
0x0: B_0x0: High speed
0x1: B_0x1: Medium speed

BLANKSEL

Bits 20-24: Comparator 3 blanking source selector This bitfield is controlled by software (if not locked). It selects the blanking source: xxxx1: TIM1 OC4 xxx1x: TIM1 OC5 xx1xx: TIM2 OC3 x1xxx: TIM3 OC3 1xxxx: TIM15 OC2.

Allowed values:
0x0: B_0x0: None (no blanking)

VALUE

Bit 30: Comparator 3 output status This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in ..

LOCK

Bit 31: COMP3_CSR register lock This bit is set by software and cleared by a system reset. It locks the whole content of the comparator 3 control register COMP3_CSR[31:0]:.

Allowed values:
0x0: B_0x0: COMP3_CSR[31:0] register read/write bits can be written by software
0x1: B_0x1: COMP3_CSR[31:0] register bits can be read but not written by software

DR

Bits 0-31: Data register bits.

IDR

Bits 0-31: General-purpose 32-bit data register bits.

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size These bits control the size of the polynomial..

Allowed values:
0x0: B_0x0: 32 bit polynomial
0x1: B_0x1: 16 bit polynomial
0x2: B_0x2: 8 bit polynomial
0x3: B_0x3: 7 bit polynomial

REV_IN

Bits 5-6: Reverse input data These bits control the reversal of the bit order of the input data.

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit reversal done by byte
0x2: B_0x2: Bit reversal done by half-word
0x3: B_0x3: Bit reversal done by word

REV_OUT

Bit 7: Reverse output data This bit controls the reversal of the bit order of the output data..

Allowed values:
0x0: B_0x0: Bit order not affected
0x1: B_0x1: Bit-reversed output format

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

Bits 0-31: Programmable polynomial.

EN1

Bit 0: DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1..

Allowed values:
0x0: B_0x0: DAC channel1 disabled
0x1: B_0x1: DAC channel1 enabled

TEN1

Bit 1: DAC channel1 trigger enable This bit is set and cleared by software to enable/disable DAC channel1 trigger. Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle..

Allowed values:
0x0: B_0x0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register
0x1: B_0x1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register

TSEL1

Bits 2-5: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: SWTRIG1
0x1: B_0x1: dac_ch1_trg1
0x2: B_0x2: dac_ch1_trg2
0xF: B_0xF: dac_ch1_trg15

WAVE1

Bits 6-7: DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. 1x: Triangle wave generation enabled Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP1

Bits 8-11: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095.

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN1

Bit 12: DAC channel1 DMA enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA mode disabled
0x1: B_0x1: DAC channel1 DMA mode enabled

DMAUDRIE1

Bit 13: DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software..

Allowed values:
0x0: B_0x0: DAC channel1 DMA Underrun Interrupt disabled
0x1: B_0x1: DAC channel1 DMA Underrun Interrupt enabled

CEN1

Bit 14: DAC channel1 calibration enable This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored..

Allowed values:
0x0: B_0x0: DAC channel1 in Normal operating mode
0x1: B_0x1: DAC channel1 in calibration mode

EN2

Bit 16: DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 disabled
0x1: B_0x1: DAC channel2 enabled

TEN2

Bit 17: DAC channel2 trigger enable This bit is set and cleared by software to enable/disable DAC channel2 trigger Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the DAC_DOR2 register takes only one dac_pclk clock cycle. These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are transferred one dac_pclk clock cycle later to the DAC_DOR2 register
0x1: B_0x1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred three dac_pclk clock cycles later to the DAC_DOR2 register

TSEL2

Bits 18-21: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 ... Refer to the trigger selection tables in for details on trigger configuration and mapping. Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: SWTRIG2
0x1: B_0x1: dac_ch2_trg1
0x2: B_0x2: dac_ch2_trg2
0xF: B_0xF: dac_ch2_trg15

WAVE2

Bits 22-23: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: wave generation disabled
0x1: B_0x1: Noise wave generation enabled

MAMP2

Bits 24-27: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. ≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 Note: These bits are available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0x1: B_0x1: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0x2: B_0x2: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0x3: B_0x3: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0x4: B_0x4: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0x5: B_0x5: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0x6: B_0x6: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0x7: B_0x7: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
0x8: B_0x8: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
0x9: B_0x9: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
0xA: B_0xA: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

DMAEN2

Bit 28: DAC channel2 DMA enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA mode disabled
0x1: B_0x1: DAC channel2 DMA mode enabled

DMAUDRIE2

Bit 29: DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 DMA underrun interrupt disabled
0x1: B_0x1: DAC channel2 DMA underrun interrupt enabled

CEN2

Bit 30: DAC channel2 calibration enable This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: DAC channel2 in Normal operating mode
0x1: B_0x1: DAC channel2 in calibration mode

SWTRIG1

Bit 0: DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

SWTRIG2

Bit 1: DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No trigger
0x1: B_0x1: Trigger

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software. They specify 12-bit data for DAC channel1..

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software. They specify 8-bit data for DAC channel1..

DACC2DHR

Bits 0-11: DAC channel2 12-bit right-aligned data These bits are written by software. They specify 12-bit data for DAC channel2..

DACC2DHR

Bits 4-15: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2..

DACC2DHR

Bits 0-7: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DACC1DHR

Bits 0-11: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 16-27: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DACC1DHR

Bits 4-15: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1..

DACC2DHR

Bits 20-31: DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2..

DACC1DHR

Bits 0-7: DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1..

DACC2DHR

Bits 8-15: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2..

DACC1DOR

Bits 0-11: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1..

DACC2DOR

Bits 0-11: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2..

DMAUDR1

Bit 13: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel1
0x1: B_0x1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

CAL_FLAG1

Bit 14: DAC channel1 calibration offset status This bit is set and cleared by hardware.

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST1

Bit 15: DAC channel1 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization)..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

DMAUDR2

Bit 29: DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: No DMA underrun error condition occurred for DAC channel2
0x1: B_0x1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is driving DAC channel2 conversion at a frequency higher than the DMA service capability rate).

CAL_FLAG2

Bit 30: DAC channel2 calibration offset status This bit is set and cleared by hardware Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: calibration trimming value is lower than the offset correction value
0x1: B_0x1: calibration trimming value is equal or greater than the offset correction value

BWST2

Bit 31: DAC channel2 busy writing sample time flag This bit is systematically set just after Sample and hold mode enable. It is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). Note: This bit is available only on dual-channel DACs. Refer to implementation..

Allowed values:
0x0: B_0x0: There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
0x1: B_0x1: There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written

OTRIM1

Bits 0-4: DAC channel1 offset trimming value.

OTRIM2

Bits 16-20: DAC channel2 offset trimming value These bits are available only on dual-channel DACs. Refer to implementation..